ddppt-yy

pysvinst

Python library for parsing module definitions and instantiations from SystemVerilog files

571project

571工程纪要

bes

book

收集专业书籍 <欢迎提交>

Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

kkndme_tianya

天涯 kkndme 神贴聊房价

lizhi

🎉 南京李志 在线播放 国内高速cdn迅雷下载

pyHDLParser

Simple Python parser for extracting HDL (VHDL or Verilog) documentation

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

svinst

Determines the modules declared and instantiated in a SystemVerilog file

vscode-verilog-hdl-support

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

Y_nvim

Y_nvim

Y_vim