davenso / fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

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Intel® FPGA Partial Reconfiguration Design Flow

This repository contains scripts, reference designs, and tutorials for the Intel FPGA Partial Reconfiguration design flow.

  • Tutorials are located in the tutorials sub directory
  • Reference Designs are located in the ref_designs sub directory
  • Scripts are located in the script sub directory

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More information available at http://www.01.org/fpga-partial-reconfig

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Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

License:MIT License


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Language:SystemVerilog 45.0%Language:C 34.2%Language:C++ 18.4%Language:Tcl 1.4%Language:Shell 0.6%Language:Makefile 0.4%Language:Mathematica 0.1%