danodus / huedeon-gpu

FPGA GPU design for DE1-SoC

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Huedeon GPU design

Triangle rasterizer with vertex-color and texturing support.

For Terasic DE1-SoC

gpu gpu2

my_video-2.mp4

Running with FuseSoC

sudo pip3 install fusesoc
fusesoc library add local .
fusesoc run --target=[TARGET] zxmarcos:huedeon:huedeon:0.0.1

Supported Targets

  • qmtech_xc7k325t_ddr3
  • de1-soc

Generate SVF from Vivado

vivado -mode batch -source data/qm_xc7k325t_ddr3_svf.cmd

About

FPGA GPU design for DE1-SoC

License:BSD 3-Clause "New" or "Revised" License


Languages

Language:C 51.0%Language:Verilog 35.8%Language:HTML 9.5%Language:C++ 1.7%Language:SystemVerilog 0.9%Language:Makefile 0.7%Language:Batchfile 0.2%Language:Mathematica 0.2%Language:Assembly 0.0%Language:Scheme 0.0%