This processor module is meant to decode the ISA of the custom "F32" CPU core used for various management tasks in many AMD Radeon GPUs.
Based on the information in radeon-tools and this presentation.
NOTE: This is a work-in-progress, and is largely unfinished. Because of this, any aspect of this plugin could change at any time. Consider yourself warned!
To do:
- Verify that the disassembly output matches that generated by
f32dis.py. - Refactor instruction decoding since it's kind of a mess right now.
- Add semantics for push/pop instructions to make the stack work.
- Handle memory accesses to the different memory spaces (define custom operations?).
- Add file loader to automatically identify old-style vs. new-style firmware images, and load without/with a 0x100 offset and with big-endian/little-endian instructions accordingly.
- Enable the file loader to add labels for the branch addresses listed in the table at the end of the firmware image.
- Adjust calling convention to match observed calling convention.
- Confirm instruction semantics on real hardware (how?).
- Confirm the register sizes and 32-bit/64-bit behavior.
- Maybe it would be better to use register aliasing with separate, aliased register names for 32/64-bit operations?
- Confirm memory byte ordering.
$ git clone https://github.com/cyrozap/ghidra-radeon-f32.git
$ cd ghidra-radeon-f32
$ gradle
The dist directory will now contain the extension zip file that you can
install into Ghidra.