Cronomantic (cronomantic)

cronomantic

Geek Repo

Location:Madrid

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Cronomantic's repositories

ZXDAAD128

DAAD interpreter created with Boriel's ZXBasic with capability to take advantage of the 128k models memory banks.

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ChooseYourDestiny

Creator for making CYOA adventures for Spectrum +3

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wb_intercon

Wishbone interconnect utilities

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async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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bouffalo_drivers

Bouffalolab lhal & rfparam & soc drivers, no pr support

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bouffalo_sdk

BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk

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buildroot_bouffalo

Linux Image for the BL808 CPU by Bouffalo Lab

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ddr3-tang-primer-20k

DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.

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divtiesus

DivTIESUS is a SD/MMC interface for the ZX Spectrum, compatible with ESXDOS. It is not a clone of Mario Pratto's DivMMC.

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duo-buildroot-sdk

Milk-V Duo Official buildroot SDK

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fx68k

FX68K version for FOSS tools

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hdmi

Send video/audio over HDMI on an FPGA

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jt12

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

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neorv32

:desktop_computer: A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

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neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

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nextz80

NextZ80

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ply

Python Lex-Yacc

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projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

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TangNano-20K-example

TangNano-20K-example

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TangPrimer-20K-example

TangPrimer-20K-example project

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usb_hid_host

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

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verilog-65C02

65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface

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verilog-axi

Verilog AXI components for FPGA implementation

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verilog-wishbone

Verilog wishbone components

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VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

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VexRiscv-verilog

Using VexRiscv without installing Scala

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wb_sdram_ctrl_32

SDRAM controller with multiple wishbone slave ports

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y80e

Y80e - Z80/Z180 compatible processor extended by eZ80 instructions

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zxbasic

The Sinclair ZX Spectrum BASIC compiler!

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