cornell-brg / pymtl

Python-based hardware modeling framework

cornell-brg/pymtl Issues

ASIC flow tutorial link is broken
Closed 3 years ago1
a small confusion of other language model support
Closed 5 years ago4
possible bug in pclib/ifcs/ValRdyBundle.py
Updated 5 years ago3
pymtl doesn't correctly register combinational blocks that write to slices of an OutPort
Closed 5 years ago2
Slice on fields in bitstruct does not produce valid Verilog
Updated 6 years ago
sext(concat()) does not translate
Updated 6 years ago
Python list slicing translation
Updated 6 years ago
Failed Installation
Closed 6 years ago1
Is it possible to generate sequential blocks in runtime?
Updated 6 years ago15
Use apt-get install flex-old instead of flex
Closed 6 years ago6
when use, there is an error list index out of range in metaclasses.py in the floder named model
Closed 6 years ago8
Help with design low-level HDL language
Updated 6 years ago
will pymtl be ported to Python3
Updated 6 years ago3
pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type
Updated 8 years ago
Verilog translation
Updated 8 years ago1
The order of test matters if this is correct.
Closed 8 years ago
The order of test matters. I think this is a bug
Updated 8 years ago
explicit_modulename doesn't work for a very simple verilog import
Updated 8 years ago3
Shall we support implicit include dependency in verilog importing?
Closed 8 years ago5
Cannot wrap a VerilogModel into a pymtl model for simulation
Closed 8 years ago4
connecting wire slice to wire slice seems not to work
Updated 9 years ago2
A minor bug (or functional extensions) of range select
Updated 9 years ago
The link to the research paper in README is wrong
Updated 9 years ago2
Verilog Translation Bug: Accessing fields from array of PortBundles not working
Updated 9 years ago
PyMTL keywords
Updated 9 years ago
Import/Translation of two identical Verilog models fails
Closed 9 years ago
Imported VerilogModel wrappers won't dump *.verilator.vcd when vcd_file is set
Updated 9 years ago
Various checker enhancements, better Error messages
Updated 9 years ago
Throw useful Error during translation when non-literal Bits constructors encountered.
Closed 9 years ago
Type inference from signal lists translate into temporaries with incorrect bitwidth
Closed 9 years ago
Gcd RTL example generates inferred latches
Updated 9 years ago1
Nested submodule and port list accesses do not translate correctly
Updated 9 years ago
Models using BitStructs don't return BitStruct objects when translated to Verilog
Closed 9 years ago
Support `s.connect()` with constant `Bits` object
Updated 9 years ago
Verilog translated models fail if using a BitStruct defined in a non-global scope
Updated 9 years ago
`TranslationTool` incorrectly uses `wire` instead of `reg` for `BitStructs`
Closed 9 years ago
SimulatorTool detects sensitivity list incorrectly for Bits in @combinational blocks
Closed 9 years ago
Add checking to detect multiple identical assignments/multiple assignments to the same signal.
Updated 9 years ago
PortBundles cannot contain lists
Updated 9 years ago
Remove verbose and confusing sensitivity list warnings.
Closed 10 years ago
Figure out a way to have a translatable truncate() function
Updated 10 years ago1
Translation tool error: zext cannot take an element of WireList
Updated 10 years ago
Add check during simulator construction for assigning to .value in @tick or .next in @combinational
Updated 10 years ago
Verilator model cache does not recompile if VCD dumping is enabled/disabled
Closed 10 years ago
Template files ending in .py cause a SyntaxError warning during install
Updated 10 years ago
Connect error message does not report which line in model caused error
Closed 10 years ago2
Using reg as module name causes verilator error
Closed 10 years ago
Add support for arithmetic right shift
Updated 10 years ago
Hard-coded path to wrapper template files for translation
Closed 10 years ago
Remove `v=` and `w=` from `__repr__`
Closed 10 years ago