CodiieSB's repositories
VHDL-2x4Decoder
The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.
VHDL-4Bit_DownCounter
A 4-bit down counter is a digital circuit that counts down from a preset value to zero, decreasing by one with each clock pulse.
VHDL-4Bit_UpCounter
A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.
VHDL-4Bit_UpDownCounter
A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.
VHDL-4x1MUX
The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.
VHDL-ArtyA7_Blinky
The code allows anyone with the Artix A7 FPGA Board to Blink the On-Board LED for any predefined Frequency.
VHDL-DFlipFlop
The VHDL code describes a D flip-flop with synchronous reset functionality.
VHDL-Half_Adder
A half adder is a digital circuit that performs addition of two binary digits, generating the sum bit and the carry bit.
VHDL-PriorityEncoder4x2
A 4x2 priority encoder is a digital circuit that takes four input lines and encodes them into a two-bit binary output based on the priority of the input lines.
VHDL-ShiftRegister
A VHDL shift register is a digital circuit implemented that allows sequential shifting of data bits either to the left or right within the register.