This project contains ply-based parsers for Liberty gate libraries and Verilog netlists. Note that these are not tested. They may only work for a subset of general grammars.
- gate functions should take input, output, and current_state vectors
- ablity to print stats for gates/library
- Master: this represents the branch currently integrated with the ROSS/gates project
- sql: utilizes an SQL database to store the object model
- py_classes: utilizes python classes to store the object model