Carrie's repositories

alu

I created an arithmetic logic unit in Verilog for a Digital Systems class

Language:VerilogStargazers:0Issues:2Issues:0
Language:JavaLicense:MITStargazers:0Issues:2Issues:0
Language:JavaLicense:NOASSERTIONStargazers:0Issues:2Issues:0
Language:JavaScriptStargazers:0Issues:0Issues:0
Language:HTMLStargazers:0Issues:2Issues:0
Language:JavaScriptStargazers:0Issues:2Issues:0

register_file

I created a 32 register system with 32 bits per register

Language:VerilogStargazers:0Issues:2Issues:0
Language:JavaLicense:MITStargazers:0Issues:2Issues:0
Stargazers:0Issues:1Issues:0
Language:JavaScriptStargazers:0Issues:0Issues:0
Language:HTMLStargazers:0Issues:2Issues:0