claint76's repositories
SIGMA
RTL implementation of Flex-DPE.
tnoc
Network on Chip Implementation written in SytemVerilog
rggen-sv-rtl
Common RTL modules for RgGen
face_recognition
The world's simplest facial recognition api for Python and the command line
nest-simulator
The NEST simulator
brian2
Brian is a free, open source simulator for spiking neural networks.
genn
GeNN is a GPU-enhanced Neuronal Network simulation environment based on code generation for Nvidia CUDA.
RenderMan
Command line C++ and Python VSTi Host library with MFCC, FFT, RMS and audio extraction and .wav writing.
auryn
Auryn: A fast simulator for spiking neural networks with synaptic plasticity
rggen-plugin-template
Project template for RgGen plugin
rggen-sv-ral
RAL class package for RgGen
dlpack
RFC for common in-memory tensor structure and operator interface for deep learning system
CeleX5-MIPI
SDK for CeleX5 sensor on CX3 platform.
PyNN
A Python package for simulator-independent specification of neuronal network models.
ANNarchy
ANNarchy (Artificial Neural Networks architect) is a parallel simulator for rate-coded and spiking neural networks.
sw
NVDLA SW
End-to-end-ASR-Pytorch
This is an open source project (formerly named Listen, Attend and Spell - PyTorch Implementation) for end-to-end ASR implemented with Pytorch, the well known deep learning toolkit.
swerv-ISS
Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
tflite
TFLite python API package for parsing TFLite model
voice_datasets
🔊 A comprehensive list of open-source datasets for voice and sound computing (40+ datasets).
s2net
Supervised Spiking Network
ASRT_SpeechRecognition
A Deep-Learning-Based Chinese Speech Recognition System 基于深度学习的中文语音识别系统
tvm
TVM integration into PyTorch
python_speech_features
This library provides common speech features for ASR including MFCCs and filterbank energies.
pytorch-memonger
Sublinear memory optimization for deep learning. https://arxiv.org/abs/1604.06174
snntoolbox_applications
Collection of Spiking Neural Network applications for SNN Toolbox.
Reed-Solomon-
This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length is of length 249 symbols and it can detect and correct upto 3 error symbols.
CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator