claint76's repositories
Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
ViterbiDecoderCpp
Viterbi decoder with vectorisation written in C++
evo
Python package for the evaluation of odometry and SLAM
ORB_SLAM2
Real-Time SLAM for Monocular, Stereo and RGB-D Cameras, with Loop Detection and Relocalization Capabilities
uciedigital
Pure digital components of a UCIe controller
verilog-ethernet
Verilog Ethernet components for FPGA implementation
opencv
Open Source Computer Vision Library
ucieanalog
An open-source UCIe implementation developed at UC Berkeley.
AES-GCM-128-192-256-bits
Configurable AES-GCM IP (128, 192, 256 bits)
BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
A-Complete-Digital-Communication-System
A simulation of a complete digital communication system with different modulation schemes in MATLAB for transmitting and receiving text messages.
acSLAM
FPGA Hardware Implementation for SLAM
reedsolomon
C library for Convolutional codes and Reed-Solomon
glow
Compiler for Neural Network hardware accelerators
maestro
An analytical cost model evaluating DNN mappings (dataflows and tiling).
pytorch-OpCounter
Count the MACs / FLOPs of your PyTorch model.
haq
[CVPR 2019, Oral] HAQ: Hardware-Aware Automated Quantization with Mixed Precision
openISP
Image Signal Processor
tensorflow-on-arm
TensorFlow for Arm
Hybrid_CDM-DFM
The pakage presents the original codes on MATLAB in Lin Sun's PJ paper.
systemrdl-compiler
SystemRDL 2.0 language compiler front-end
verilog-axi
Verilog AXI components for FPGA implementation
simple-camera-pipeline
A simple and light-weight camera image processing pipeline
axi4_vip
Verification IP for APB protocol
MatRaw
Read and Process Camera Raw Data with MATLAB
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
tvip-axi
AMBA AXI VIP