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chl218 / Digital-Systems-Laboratory

Digital system designs with SystemVerilog

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Digital-Systems-Laboratory

  • Project 1: Alarm Clock
  • Project 2: Robertson's Multiplication Algorithm
  • Project 3:
    • Part 1: Traffic Light
    • Part 2: Pseudo-random Number Generator
  • Project 4: LFSR encoder
  • Project 5: LFSR decoder

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Digital system designs with SystemVerilog

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Language:SystemVerilog 100.0%