chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Home Page:https://chipsalliance.github.io/sv-tests-results/

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BlackParrot setup for UhdmYosys

alaindargelas opened this issue · comments

For plain Surelog, the command line contains -lowmem and --top-module:

surelog -nopython -parse -nonote -noinfo -nowarning -sverilog --top-module bp_be_top -lowmem .....

For uhdmyosys, both options are missing (Yielding an out of memory):

surelog -nopython -nobuiltin -parse -sverilog -nonote -noinfo -nowarning ....

Should BlackParrot be moved the "Cores" list in sv-tests?

Both issues have been addressed, thanks