ERROR: Constrained pad W5 is not in available pad map

[Adam Taylor]

Yesterday I installed the f4pga command line python tool and tested it on a very simple design. I got the following error:
log.txt

Previous to this attempt, I have been able to get the same verilog and xdc file to compile to a working basys3 bitstream via Edalize/F4PGA

The command I ran was f4pga build -f flow.json and the files are as follows:

blinky.v:

module blinky
  #(parameter clk_freq_hz = 100000000)
   (input  clk,
    output reg q = 1'b0);

   reg [$clog2(clk_freq_hz)-1:0] count = 0;

   always @(posedge clk) begin
      count <= count + 1;
      if (count == clk_freq_hz - 1) begin
         q <= !q;
         count <= 0;
      end
   end

endmodule

blinky.xdc:

## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_34 Sch=CLK100MHZ
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000}  [get_ports { clk }];
create_clock -period 10.000 [get_ports { clk }];

## LED
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L23N_T3_A02_D18_14 Sch=led[0]

## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

flow.json:

{
    "default_platform" : "xc7a50t",
    "dependencies" : {
        "sources" : ["blinky.v"],
        "xdc" : ["blinky.xdc"],
        "synth_log" : "synth.log",
        "pack_log" : "pack.log"
    },
    "values" : {
        "top" : "blinky"
    },
    "xc7a50t" : {
        "default_target" : "bitstream",
        "dependencies" : {
            "build_dir" : "build/arty_35"
        }
    }
}

[Adam Taylor]

I went to the xc7a50t.json files and made a few edits including changing the default paackage from csg324-1 to cpg236-1 (which is the basys3 that I'm using) and I get a different error this time:

log.txt

[Adam Taylor]

I was able to get past this step by editing the xc7a50t.json file that is a part of the f4pga toolchain. Under values -> part_name I updated it to the correct package that I'm compiling for, xc7a35tcpg236-1 instead of xc7a35tcsg324-1. I got past that point but there's still another issue, this time it looks like a python issue which I don't quite understand.
log.txt

[Adam Taylor]

I also have discovered that the error has to do with the .symbicache file that lives in the directory. Removing the file allows the f4pga tool to move past the error mentioned in my most recent comment (the python runtime error).

[Adam Taylor]

I now have been able to use the tool to build a bitstream, but it's not doing anything on the board. I'm wondering if maybe the constraints are not being loaded correctly. If the previous issues get resolved I might open a new issue.

[Adam Taylor]

The original constraints issue was fixed by 9b140e9