Probes should print more information about why types are non-equivalent

[Jack Koenig]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Consider the following example:

//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.4.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.probe._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Foo extends Module {
  val out = IO(Output(Probe(UInt(8.W))))

  val w = Wire(UInt(6.W))

  define(out, ProbeValue(w))
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

This errors with:

[error] Users/koenig/work/t/define/chisel-example.scala 16:9: Cannot define a probe on a non-equivalent type.
[error] There were 1 error(s) during hardware elaboration.

What is the expected behavior?

It would be nice if the error message would include some information about how the types differ. This is especially important for Bundles with mismatched fields deeply nested.

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?