ChiselSim does not properly support views (e.g. FlatIO)
jackkoenig opened this issue · comments
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Try the following code:
//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.3.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.3.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
import chisel3._
import chisel3.simulator.EphemeralSimulator._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage
class Foo extends Module {
val io = FlatIO(new Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
})
val delay = RegNext(io.in)
io.out := delay
}
object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
simulate(new Foo) { c =>
c.io.in.poke(12.U)
c.clock.step()
c.io.out.peek()
}
}What is the current behavior?
Verilog generates just fine, but ChiselSim throws an exception:
Exception in thread "main" java.util.NoSuchElementException: key not found: Foo.in: IO[UInt<8>]
at scala.collection.immutable.Map$Map4.apply(Map.scala:535)
at chisel3.simulator.package$AnySimulatedModule.port(package.scala:36)
at chisel3.simulator.PeekPokeAPI$testableData.poke(PeekPokeAPI.scala:116)
at chisel3.simulator.PeekPokeAPI$testableData.poke(PeekPokeAPI.scala:111)
What is the expected behavior?
This should work just fine
Please tell us about your environment:
Other Information
Derived from question on Gitter1.
What is the use case for changing the behavior?
Correct behavior