FixedIO__Module doesn't work with Probe-type top-level ports
mwachs5 opened this issue · comments
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
class Agg extends Bundle {
val foo = Bool()
val bar = Bool()
}
class FixedIO extends Bundle {
val elem = Probe(Bool())
val agg = Probe(new Agg())
}
class ExampleRaw extends FixedIORawModule[FixedIO](new FixedIO()) {
val elemWire = Wire(Bool())
elemWire := false.B
probe.define(io.elem, probe.ProbeValue(elemWire))
val aggWire = Wire(new Agg())
aggWire := DontCare
probe.define(io.agg, probe.ProbeValue(aggWire))
}
class ExampleExt extends FixedIOExtModule[FixedIO](new FixedIO())
class Parent extends Module {
val childRaw = Module(new ExampleRaw())
val childExt = Module(new ExampleExt())
val outElemRaw = IO(Bool())
val probeElemWireRaw = Wire(Probe(Bool()))
outElemRaw := probe.read(probeElemWireRaw)
probeElemWireRaw :<>= childRaw.io.elem
val probeElemWireExt = Wire(Probe(Bool()))
val outElemExt = IO(Bool())
outElemExt := probe.read(probeElemWireExt)
probeElemWireExt :<>= childExt.io.elem
val outAggRaw = IO(new Agg())
val probeAggWireRaw = Wire(Probe(new Agg()))
outAggRaw := probe.read(probeAggWireRaw)
probeAggWireRaw :<>= childRaw.io.agg
val probeAggWireExt = Wire(Probe(new Agg()))
val outAggExt = IO(new Agg())
outAggExt := probe.read(probeAggWireExt)
probeAggWireExt :<>= childExt.io.agg
}
What is the current behavior?
What is the expected behavior?
This should work -- we should be able to connect to the FixedIOModule as we would to a not-fixed-IO module with probe ports.
Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
Making FixedIO___Modules fully featured
Note that this also does not currently work to have Aggregates which contain Probes within a FixedIORawModule.