chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Home Page:https://www.chisel-lang.org/

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Connectable does not properly handle Views

jackkoenig opened this issue · comments

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Run the following Scala CLI, using current head of main (same bug exists in v6.3.0):

//> using repository "sonatype-s01:snapshots"
//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:7.0.0-M1+76-03ef61f3-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M1+76-03ef61f3-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.experimental.dataview._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class MyBundle(cond: Boolean) extends Bundle {
  val foo = UInt(8.W)
  val realBar = Option.when(cond)(UInt(8.W))
  def bar = realBar.map(_.viewAs)
}

class Foo extends Module {
  val in = IO(Input(new MyBundle(true)))
  val out = IO(Output(new MyBundle(false)))

  out :<>= in.waiveEach { case b: MyBundle => b.bar.toSeq }
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

This will error with:

[error] .../example.scala 22:7: dangling producer field Foo.in.realBar: IO[UInt<8>]

What is the expected behavior?

If you change the waiver to use .realBar instead of .bar, then the code properly waives the existence of realBar and generates Verilog. Since bar is just a view of realBar, the behavior should be identical when waiving bar.

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?