Chisel6.0 multiplication Width Lint Errors

[ShiyangPeng]

BUG Report

when i try to use Chisel6.0 to implement a multiplication as code

object Main extends App {
  ChiselStage.emitSystemVerilogFile(new UInt_mul(),
    Array("help"),
    Array("--disable-all-randomization", "-strip-debug-info","--lowering-options=disallowLocalVariables"),
  )
}
class UInt_mul extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt(8.W))
    val b = Input(UInt(8.W))

    val c = Output(UInt(8.W))
  })
  val mul_reg = RegInit(0.U(8.W))
  mul_reg := (io.a * io.b)(15,8)
  io.c := mul_reg
}

it will generate verilog code like

reg  [7:0]  mul_reg;
  wire [15:0] _mul_reg_T = {8'h0, io_a} * {8'h0, io_b};
  always @(posedge clock) begin
    if (reset)
      mul_reg <= 8'h0;
    else
      mul_reg <= _mul_reg_T[15:8];
  end // always @(posedge)
  assign io_c = mul_reg;

it means that a 16x16 DSP slice will be used for this cell ,rather than 8x8 DSP slice.obviously it is a large waste in fpga project
i got expect verilog code if i use chisle3.0

  reg [7:0] mul_reg; // @[UInt_mul.scala 10:24]
  wire [15:0] _mul_reg_T = io_a * io_b; // @[UInt_mul.scala 11:20]
  assign io_c = mul_reg; // @[UInt_mul.scala 12:8]
  always @(posedge clock) begin
    if (reset) begin // @[UInt_mul.scala 10:24]
      mul_reg <= 8'h0; // @[UInt_mul.scala 10:24]
    end else begin
      mul_reg <= _mul_reg_T[15:8]; // @[UInt_mul.scala 11:11]
    end
  end

i note that it maybe a bug of firtool , so i fond same condition in this issue
can be solve by Chisel6.0 ? it not occure with Chisel3.0

[Hideto Ueno]

It's not fixed yet. I had a branch to fix so will submit a PR for CIRCT.