Layers are not emitted unless a block exists

[Schuyler Eldridge]

The use of a layer in a layer colored probe or with an enable layer isn't enough to have Chisel internals cause the layer to be emitted. Consider the following example:

//> using scala "2.13.11"
//> using repository sonatype-s01:snapshots
//> using lib "org.chipsalliance::chisel::7.0.0-M1+55-ea2d1036-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::7.0.0-M1+55-ea2d1036-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.probe.Probe
import chisel3.layer.{Layer, Convention, enable}
import circt.stage.ChiselStage

object LayerA extends Layer(Convention.Bind)

class Foo extends RawModule {
  val a = IO(Output(Probe(UInt(1.W), LayerA)))
  enable(LayerA)
}

object Main extends App {
  println(ChiselStage.emitCHIRRTL(new Foo))
}

This produces the following illegal FIRRTL:

FIRRTL version 4.0.0
circuit Foo :
  public module Foo enablelayer LayerA :
    output a : Probe<UInt<1>, LayerA>

    skip

h/t @nandor for finding this issue.