Preprocessor Constants

[Hazem Al Indari]

Hello there,

I am still new to chisel so this might be already a feature but am not aware of!

Is there a way in chisel to have something similar to what C offers with preprocessor defines (for example #define DEBUG 1) to be used with printf statements? currently I am using an object construct

object Settings {
val bufferSize = 256
val DEBUG = false
val XXX = true
}
and then in my module I use the following
if (Settings.DEBUG) {
printf("Debug signal example\n")
}

but this also doesn't work with chisel statements like
if (Settings.XXX) {val tmpReg = RegInit(0.U(w.W))}
I get an error stating:
[error] file1.scala:111:7: not found: value tmpReg
[error] tmpReg := input1_in_bufferReg(0)

thank you in advance

[Jack Koenig]

Howdy!

There is no String-y preprocessor for Chisel; however, you can do what you are trying to do here, you just need to treat your if statements as regular code rather than thinking about them as preprocessor defines. Chisel is fundamentally metaprogramming--you are writing a Scala program that executes and the execution of that program constructs the hardware you are trying to create.

For your specific example, you have to return the tmpReg from your if block (note that in Scala, you don't use an explicit return keyword, the last statement in a block is the returned value). Since the existence of this register is optional depending on the parameter, you wrap it in an Option:

val tmpReg = if (Settings.XXX) {
  Some(RegInit(0.U(w.W)))
} else {
  None
}
// later in the file
if (tmpReg.isDefined) { // You could also do if (Settings.XXX)
  tmpReg.get := input1_in_bufferReg(0)
}

The optionality of tmpReg is explicit (and type-checked by the compiler to help you avoid bugs) rather than magically there or not based on String substitution.

Now this may feel very boilerplate-y, and it can be if you write it like one would write Python or C, but if you adopt a more Scala-y, functional style, you could write it as something like:

val tmpReg = Option.when(Settings.XXX)(RegInit(0.U(w.W)))
// later in the file
tmpReg.foreach(_ := input1_in_bufferReg(0))

[Hazem Al Indari]

Thank you, this solves the problem