`PanamaCIRCTConverter` emits incorrect firrtl for negative `SInt` literals.

[Ocean Shen]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:
When developing integration tests for it (#3936), I noticed the following case will fail:

class WireAndReg extends Module {
  val r = IO(Input(Bool()))
  val o = IO(Output(UInt(2.W)))

  val o_next = RegInit(false.B)
  val flip = Reg(Bool())
  val magic = Wire(SInt(8.W))

  o := o_next && magic(7)
  o_next := flip
  flip := flip ^ r
  magic := -42.S
}

println(lit.utility.panamaconverter.firrtlString(new WireAndReg))

What is the current behavior?
For Wire magic, PanamaConverter will emit connect magic, pad(SInt<7>(22), 8). For some reason, the sign bit is truncated, and in Verilog generation the whole circuit will be optimized out.

What is the expected behavior?
For reference, circt.stage.ChiselStage.emitCHIRRTL emits connect magic, asSInt(UInt<7>(0h56)).

Please tell us about your environment:

nix develop shell on HEAD as of 31b222e.

What is the use case for changing the behavior?

Give correct negative SInts.

[Ocean Shen]

@SpriteOvO could probably look into this?

[Asuna]

I'll look into it tonight, thanks for report.