chipsalliance / aib-protocols

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axi4-mm addr width cover point not correct

nij-intel opened this issue · comments

covergroup aximm_cov;
aximm_datawidth_cov : coverpoint aximm_cov_datawidth {
bins aximm_datawidth_bin[] = {32,64,128,256,512};
}
aximm_addrwidth_cov : coverpoint aximm_cov_addrwidth {
bins aximm_addrwidth_bin[] = {32,64,128,256,512};
}

I think this should {32,48} can you please review rest of the cover points to make sure it is aligning with DUT

Fixed in 0.9.8 drop

aximm_addrwidth_cov : coverpoint aximm_cov_addrwidth {
bins aximm_addrwidth_bin[] = {32,64};
}

should include 48?

This issue should be fixed in the Feb 18 release.

fixed in 1.0