AXIMM synthesis not optimizing unused pipeline registers

[nij-intel]

on tb_mh2.1_sh1_64 test case: single channel AXIMM synthesis preserves unused registers:

Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_39__axi_mm_master_concat_rx_phy_flop_0_reg_reg_74__axi_mm_master_concat_rx_phy_flop_0_reg_reg_75__axi_mm_master_concat_rx_phy_flop_0_reg_reg_79_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_0__axi_mm_master_concat_tx_phy_flop_0_reg_reg_1__axi_mm_master_concat_tx_phy_flop_0_reg_reg_4__axi_mm_master_concat_tx_phy_flop_0_reg_reg_53_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_54__axi_mm_master_concat_tx_phy_flop_0_reg_reg_55__axi_mm_master_concat_tx_phy_flop_0_reg_reg_56__axi_mm_master_concat_tx_phy_flop_0_reg_reg_57_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_58__axi_mm_master_concat_tx_phy_flop_0_reg_reg_59__axi_mm_master_concat_tx_phy_flop_0_reg_reg_60__axi_mm_master_concat_tx_phy_flop_0_reg_reg_61_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_62__axi_mm_master_concat_tx_phy_flop_0_reg_reg_63__axi_mm_master_concat_tx_phy_flop_0_reg_reg_64__axi_mm_master_concat_tx_phy_flop_0_reg_reg_65_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_66__axi_mm_master_concat_tx_phy_flop_0_reg_reg_67__axi_mm_master_concat_tx_phy_flop_0_reg_reg_68__axi_mm_master_concat_tx_phy_flop_0_reg_reg_69_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_70__axi_mm_master_concat_tx_phy_flop_0_reg_reg_71__axi_mm_master_concat_tx_phy_flop_0_reg_reg_72__axi_mm_master_concat_tx_phy_flop_0_reg_reg_73_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'll_transmit_iar_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_2__ll_transmit_iaw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_0__ll_transmit_iaw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_1__ll_transmit_iaw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_2_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'll_transmit_iw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_0__ll_transmit_iw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_1__ll_transmit_iw_ll_tx_cred_ii_actual_asym_credit_usage_reg_reg_2__ll_transmit_iw_ll_tx_cred_ii_txonline_dly2_reg' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_0__axi_mm_master_concat_rx_phy_flop_0_reg_reg_1__axi_mm_master_concat_rx_phy_flop_0_reg_reg_73__axi_mm_master_concat_rx_phy_flop_0_reg_reg_76_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_78__axi_mm_master_concat_tx_phy_flop_0_reg_reg_2__axi_mm_master_concat_tx_phy_flop_0_reg_reg_5__axi_mm_master_concat_tx_phy_flop_0_reg_reg_52_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_32__axi_mm_master_concat_rx_phy_flop_0_reg_reg_33__axi_mm_master_concat_rx_phy_flop_0_reg_reg_34__axi_mm_master_concat_rx_phy_flop_0_reg_reg_35_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_36__axi_mm_master_concat_rx_phy_flop_0_reg_reg_37__axi_mm_master_concat_rx_phy_flop_0_reg_reg_38__axi_mm_master_concat_rx_phy_flop_0_reg_reg_40_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_41__axi_mm_master_concat_rx_phy_flop_0_reg_reg_42__axi_mm_master_concat_rx_phy_flop_0_reg_reg_43__axi_mm_master_concat_rx_phy_flop_0_reg_reg_44_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_45__axi_mm_master_concat_rx_phy_flop_0_reg_reg_46__axi_mm_master_concat_rx_phy_flop_0_reg_reg_47__axi_mm_master_concat_rx_phy_flop_0_reg_reg_48_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_49__axi_mm_master_concat_rx_phy_flop_0_reg_reg_50__axi_mm_master_concat_rx_phy_flop_0_reg_reg_51__axi_mm_master_concat_rx_phy_flop_0_reg_reg_56_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_52__axi_mm_master_concat_rx_phy_flop_0_reg_reg_53__axi_mm_master_concat_rx_phy_flop_0_reg_reg_54__axi_mm_master_concat_rx_phy_flop_0_reg_reg_55_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_57__axi_mm_master_concat_rx_phy_flop_0_reg_reg_58__axi_mm_master_concat_rx_phy_flop_0_reg_reg_59__axi_mm_master_concat_rx_phy_flop_0_reg_reg_60_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_61__axi_mm_master_concat_rx_phy_flop_0_reg_reg_62__axi_mm_master_concat_rx_phy_flop_0_reg_reg_63__axi_mm_master_concat_rx_phy_flop_0_reg_reg_64_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_65__axi_mm_master_concat_rx_phy_flop_0_reg_reg_66__axi_mm_master_concat_rx_phy_flop_0_reg_reg_67__axi_mm_master_concat_rx_phy_flop_0_reg_reg_68_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_69__axi_mm_master_concat_rx_phy_flop_0_reg_reg_70__axi_mm_master_concat_rx_phy_flop_0_reg_reg_71__axi_mm_master_concat_rx_phy_flop_0_reg_reg_72_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_8__axi_mm_master_concat_rx_phy_flop_0_reg_reg_9__axi_mm_master_concat_rx_phy_flop_0_reg_reg_10__axi_mm_master_concat_rx_phy_flop_0_reg_reg_12_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_22__axi_mm_master_concat_rx_phy_flop_0_reg_reg_24__axi_mm_master_concat_rx_phy_flop_0_reg_reg_25__axi_mm_master_concat_rx_phy_flop_0_reg_reg_26_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_27__axi_mm_master_concat_rx_phy_flop_0_reg_reg_28_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_2__axi_mm_master_concat_rx_phy_flop_0_reg_reg_3__axi_mm_master_concat_rx_phy_flop_0_reg_reg_4__axi_mm_master_concat_rx_phy_flop_0_reg_reg_5_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_6__axi_mm_master_concat_rx_phy_flop_0_reg_reg_7__axi_mm_master_concat_tx_phy_flop_0_reg_reg_6__axi_mm_master_concat_tx_phy_flop_0_reg_reg_7_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_8__axi_mm_master_concat_tx_phy_flop_0_reg_reg_9__axi_mm_master_concat_tx_phy_flop_0_reg_reg_10__axi_mm_master_concat_tx_phy_flop_0_reg_reg_11_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_12__axi_mm_master_concat_tx_phy_flop_0_reg_reg_13__axi_mm_master_concat_tx_phy_flop_0_reg_reg_20__axi_mm_master_concat_tx_phy_flop_0_reg_reg_21_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_22__axi_mm_master_concat_tx_phy_flop_0_reg_reg_23__axi_mm_master_concat_tx_phy_flop_0_reg_reg_24__axi_mm_master_concat_tx_phy_flop_0_reg_reg_25_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_26__axi_mm_master_concat_tx_phy_flop_0_reg_reg_27__axi_mm_master_concat_tx_phy_flop_0_reg_reg_28__axi_mm_master_concat_tx_phy_flop_0_reg_reg_29_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_30__axi_mm_master_concat_tx_phy_flop_0_reg_reg_31__axi_mm_master_concat_tx_phy_flop_0_reg_reg_32__axi_mm_master_concat_tx_phy_flop_0_reg_reg_33_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_34__axi_mm_master_concat_tx_phy_flop_0_reg_reg_35__axi_mm_master_concat_tx_phy_flop_0_reg_reg_36__axi_mm_master_concat_tx_phy_flop_0_reg_reg_37_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_38__axi_mm_master_concat_tx_phy_flop_0_reg_reg_40__axi_mm_master_concat_tx_phy_flop_0_reg_reg_41__axi_mm_master_concat_tx_phy_flop_0_reg_reg_42_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_43__axi_mm_master_concat_tx_phy_flop_0_reg_reg_44__axi_mm_master_concat_tx_phy_flop_0_reg_reg_45__axi_mm_master_concat_tx_phy_flop_0_reg_reg_46_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_47__axi_mm_master_concat_tx_phy_flop_0_reg_reg_48__axi_mm_master_concat_tx_phy_flop_0_reg_reg_49__axi_mm_master_concat_tx_phy_flop_0_reg_reg_50_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_11__axi_mm_master_concat_rx_phy_flop_0_reg_reg_13__axi_mm_master_concat_rx_phy_flop_0_reg_reg_14__axi_mm_master_concat_rx_phy_flop_0_reg_reg_15_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_rx_phy_flop_0_reg_reg_16__axi_mm_master_concat_rx_phy_flop_0_reg_reg_17__axi_mm_master_concat_rx_phy_flop_0_reg_reg_18__axi_mm_master_concat_rx_phy_flop_0_reg_reg_19_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_3__axi_mm_master_concat_tx_phy_flop_0_reg_reg_14__axi_mm_master_concat_tx_phy_flop_0_reg_reg_15__axi_mm_master_concat_tx_phy_flop_0_reg_reg_16_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'axi_mm_master_concat_tx_phy_flop_0_reg_reg_17__axi_mm_master_concat_tx_phy_flop_0_reg_reg_18__axi_mm_master_concat_tx_phy_flop_0_reg_reg_19__axi_mm_master_concat_tx_phy_flop_0_reg_reg_51_' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'll_transmit_iar_ll_tx_cred_ii_potential_asym_credit_usage_reg_reg_3__ll_transmit_iar_ll_tx_cred_ii_rx_credit_enc_asym_reg_1__ll_transmit_iar_ll_tx_cred_ii_rx_credit_enc_asym_reg_2__ll_transmit_iar_ll_tx_cred_ii_tx_coal_tx_credit_reg_reg' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', cell 'll_transmit_iw_ll_tx_cred_ii_potential_asym_credit_usage_reg_reg_3__ll_transmit_iw_ll_tx_cred_ii_rx_credit_enc_asym_reg_1__ll_transmit_iw_ll_tx_cred_ii_rx_credit_enc_asym_reg_2__ll_transmit_iw_ll_tx_cred_ii_tx_coal_tx_credit_reg_reg' does not drive any nets. (LINT-1)
Warning: In design 'axi_mm_master_top', port 'm_gen2_mode' is not connected to any nets. (LINT-28)