AXI4-MM regression failures

Question

AXI4-MM regression failures

nij-intel opened this issue 3 years ago · comments

regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR : regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR : 5
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR : regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR : regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 3
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nij-intel · Answer 1 · Wed Dec 22 2021 04:44:43 GMT+0800 (China Standard Time)

With more details:

egrep -E "UVM_ERROR\s*|UVM_FATAL\s*|UVM_WARNING\s*" regression/test*/logs/.log | egrep -v ":\s0"
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3911500: reporter [is_valid] Invalid wstrb[1] of 0xfd29 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3911500: reporter [is_valid] Invalid wstrb[2] of 0xe70c0000 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3911500: reporter [is_valid] Invalid wstrb[3] of 0xbeec provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3911500: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:valid_write_strobe_check] Description: Monitor Check that valid Write Strobes are driven for each data beat!
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : 3
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 1
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 4505000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d0) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('hb) SECURE('d1) ADDR('hf045e7bb) CACHE_TYPE('d0) START_TIME(3344000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 4482000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d7) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h1) SECURE('d1) ADDR('hdc278dd9) CACHE_TYPE('d0) START_TIME(3366000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13345000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100001) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(CLEANSHAREDPERSIST) ID('h9) SECURE('d1) ADDR('hc51637e7a187) CACHE_TYPE('d14) START_TIME(3211000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13347000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READONCEMAKEINVALID) ID('h1) SECURE('d0) ADDR('h447fe45cdf43) CACHE_TYPE('d15) START_TIME(3319000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50001000
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50001000
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13393000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100000) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(CLEANSHAREDPERSIST) ID('h7) SECURE('d1) ADDR('h71130926) CACHE_TYPE('d0) START_TIME(2587000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13401000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100007) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(DVMMESSAGE) ID('h3) SECURE('d1) ADDR('hf05878d8) CACHE_TYPE('d10) START_TIME(3354000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_070__tb_mh2_sh2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
Binary file regression/test_096__tb_mh2_sh2__tx_strobe_loc_147/logs/sim_directed_test_m2s2.log matches
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50001000
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50001000
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 4558000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h1) SECURE('d1) ADDR('h6a0e1c02) CACHE_TYPE('d0) START_TIME(3446000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 4556000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d11) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('he) SECURE('d1) ADDR('haed739e0) CACHE_TYPE('d0) START_TIME(3470000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_100__tb_mh2_sh2__tx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 3424000: uvm_test_top.axi_env.axi_system_env.master[0] [sample()] Saw rvalid assertion for id 'h0. But, no corresponding transaction found
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 3464000: uvm_test_top.axi_env.axi_system_env.master[0] [sample()] Saw rvalid assertion for id 'h0. But, no corresponding transaction found
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3470000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(CLEANINVALID) ID('h0) SECURE('d0) ADDR('h1a4fc9c0) CACHE_TYPE('d7) START_TIME(3246000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3478000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(CLEANINVALID) ID('h0) SECURE('d0) ADDR('h1a4fc9c0) CACHE_TYPE('d7) START_TIME(3246000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3482000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(CLEANINVALID) ID('h0) SECURE('d0) ADDR('h1a4fc9c0) CACHE_TYPE('d7) START_TIME(3246000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3484000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(CLEANINVALID) ID('h0) SECURE('d0) ADDR('h1a4fc9c0) CACHE_TYPE('d7) START_TIME(3246000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3490000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(CLEANINVALID) ID('h0) SECURE('d0) ADDR('h1a4fc9c0) CACHE_TYPE('d7) START_TIME(3246000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3440000: uvm_test_top.axi_env.axi_system_env.master[0].monitor [register_fail:AMBA:AXI3:rlast_asserted_for_last_read_data_beat] Description: Monitor Check that RLAST is HIGH only for the last beat of READ burst ! - xact {OBJECT_NUM('d6) PORT_ID('d0) PORT_NAME() TYPE(READ) COHERENT_XACT_TYPE(WRITEEVICT) ID('h5) SECURE('d0) ADDR('h811eed9) CACHE_TYPE('d11) START_TIME(3258000)}
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1478) @ 3440000: uvm_test_top.aximm_scb [compare_transaction_field] Burst length mismatch: m_xact: 3 && s_xact: 6
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1484) @ 3440000: uvm_test_top.aximm_scb [compare_transaction_field] burst_size mismatch: m_xact: BURST_SIZE_128BIT && s_xact: BURST_SIZE_64BIT
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1486) @ 3440000: uvm_test_top.aximm_scb [compare_transaction_field] burst_type mismatch: m_xact: INCR && s_xact: FIXED
regression/test_102__tb_mq2_sq2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 2
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3494000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 75aa86c53b508e0ee19c352e50bf7e4dbc72af24dea76896ef66e868229e430fec906b6dcc739c9a9d3c96d23f5a1d17b29880b1451d7f076c7a0dbb9c7d4b3d && s_xact: 75aa86c53b508e0ee19c352e54bf7e4dbc72af24dea76896ef66e868229e430fec906b6dcc739c9a9d3c96d23f5a1d17b29880b1451d7f076c7a0dbb9c7d4b3d
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4004000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: e156dc5dbad4e93ac311579ae255c4b63bd22ebbbc3e676fb57b462434b1cbe6335b5b46fbc6e1d6a2f1e737f6249f32e10501da226fc89db5d03faf1d7ab3c3 && s_xact: e156dc5dbad4e93ac311579ae655c4b63bd22ebbbc3e676fb57b462434b1cbe6335b5b46fbc6e1d6a2f1e737f6249f32e10501da2a6fc89db5d03faf1d7ab3c3
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 5024000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: b266e02e7cfe44bad34b3a5b23da8618bafd149143a801e9abec2e22ee83c17aa234d909b7b2542f3b81340b6833dc87ab57a7c691fafe7ccd955a2834339a49 && s_xact: b266e02e7cfe44bad34b3a5b27da8618bafd149143a801e9abec2e22ee83c17aa234d909b7b2542f3b81340b6833dc87ab57a7c691fafe7ccd955a2834339a49
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 5528000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 588697c0cfad232bc471c525c0b468a3c858c97f705deb96841f64c0a76cdbf6d3f908aeb12642a20f394c198293fd3f587186c311ec2df0b53903d41316a413 && s_xact: 588697c0cfad232bc471c525c4b468a3c858c97f705deb96841f64c0a76cdbf6d3f908aeb12642a20f394c198293fd3f587186c311ec2df0b53903d41316a413
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 5786000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: a50712bd37787cfc97b7a31170b99dd5d126d1144dfb2864d8e642193f99521b226ab195244703e90a4314fd348fc60614707921441ddfd9365dc2e574e415b1 && s_xact: a50712bd37787cfc97b7a31174b99dd5d126d1144dfb2864d8e642193f99521b226ab195244703e90a4314fd348fc60614707921441ddfd9365dc2e574e415b1
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_directed_test_m2s2.log:UVM_ERROR : 5
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_108__tb_mq2_sq2__data_width_512/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23708000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100001) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READNOTSHAREDDIRTY) ID('h2) SECURE('d1) ADDR('hcb3d4aed68b) CACHE_TYPE('d11) START_TIME(3384000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23686000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100008) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READONCE) ID('hd) SECURE('d0) ADDR('h3b3778ac7117) CACHE_TYPE('d0) START_TIME(3686000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_109__tb_mq2_sq2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 1
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3882000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: bb7a59db3042c99a1830057629771b5384baf86c965f60b7e3dce0bb75d3338ea290d25d7a155a2aede7d7691065291b2801f5ff52bc4cacb875ebbf83b86683 && s_xact: bb7a59db3042c9da1830057629771b5384baf86c965f60b7e3dce0bb75d3338ea290d25d7a155a2aede7d7691065291b2801f5ff52bc4cacb875ebbf83b86683
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4118000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 9e01c7445fb23ea1c718a25c06a02424830efc48353610e65df90b96fb756fc0c2cf8404551473c66d109754a62ba95174581980e8741a22f6445f50c7ba18db && s_xact: 9e01c7445fb23ee1c718a25c06a02424830efc48353610e65df90b96fb756fc0c2cf8404551473c66d109754a62ba9d174581980e8741a22f6445f50c7ba18db
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4366000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: ed2d186bf837bf01c8a52ac93ca20ea2ba77283ad20301464084d08d00adae8b477847e110771993c4b1ca9a12dade0ed1c3dbe22615d15477838ce8b5f52c46 && s_xact: ed2d186bf837bf41c8a52ac93ca20ea2ba77283ad20301464084d08d00adae8b477847e110771993c4b1ca9a12dade0ed1c3dbe22615d15477838ce8b5f52c46
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4606000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 5c87092c801a460f026636439394e1d8c0d51dcd96da46bfb17762d783c4df5eb1cbf8fc40afceab112612e679052b182716ec1d12b88b83f052c51ef712dfbc && s_xact: 5c87092c801a460f026636439394e1d8c0d51dcd96da46bfb17762d783c4df5eb1cbf8fc40afceab112612e679052b982716ec1d12b88b83f052c51ef712dfbc
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4844000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 253211249640edaa0f30cc40546d6b8cfe94bf846b1a59b2544351478203a0bccea292b7cad644e0dde5dda3230bf541ef6c40bc225a2c26af53dc96cf1dbab3 && s_xact: 253211249640edea0f30cc40546d6b8cfe94bf846b1a59b2544351478203a0bccea292b7cad644e0dde5dda3230bf5c1ef6c40bc225a2c26af53dc96cf1dbab3
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_directed_test_m2s2.log:UVM_ERROR : 5
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3878000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: b718707c86355b8962919519e5a3bfc2b14256799367b71a6851e4f534d0e925b5e61ee4497efcdfa63a846b00ee1e7784bab11c839ba9a492e078175185cb8b && s_xact: b718707c86355bc962919519e5a3bfc2b14256799367b71a6851e4f534d0e925b5e61ee4497efcdfa63a846b00ee1e7784bab11c839ba9a492e078175185cb8b
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3878000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: c3531b7c967252157c01adc83a94c6b74836081614fc348fb91b6b0254ab42a739de5902eb78f0734146d6a78e7aa56232d480d586935a03b735c72abdbf78cb && s_xact: c3531b7c967252557c01adc83a94c6b74836081614fc348fb91b6b0254ab42a739de5902eb78f0734146d6a78e7aa5e232d480d586935a03b735c72abdbf78cb
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3878000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: dcb1c739bfe5da2fdc306c151f2cbd0dd7683095afc041a5cb03f7828ce31290af1cfaa056dd38d52cd5249ed54b9f433ce67276aa28cc25ae34ab4dd03a6b84 && s_xact: dcb1c739bfe5da6fdc306c151f2cbd0dd7683095afc041a5cb03f7828ce31290af1cfaa056dd38d52cd5249ed54b9fc33ce67276aa28cc25ae34ab4dd03a6b84
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3878000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 49bc99622a94310850ae09e59fc3efb0bc6ae6a7f857687f197de282c10339e621ad745661c367b176e842e7d39673480164f248823f49703ca7010b98d1ee7a && s_xact: 49bc99622a94310850ae09e59fc3efb0bc6ae6a7f857687f197de282c10339e621ad745661c367b176e842e7d39673c80164f248823f49703ca7010b98d1ee7a
regression/test_110__tb_mq2_sq2__rx_dbi_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
Binary file regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_directed_test_m2s2.log matches
regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5926000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d1) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h9) SECURE('d1) ADDR('hc336594a6e1f) CACHE_TYPE('d0) START_TIME(3486000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5834000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d12) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('hb) SECURE('d1) ADDR('h4c1e5ce9f59b) CACHE_TYPE('d0) START_TIME(3530000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_115__tb_mq2_sq2__rx_perst_marker_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 4
regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_119__tb_mq2_sq2__rx_strobe_loc_5/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23508000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100001) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READCLEAN) ID('h3) SECURE('d1) ADDR('hdad5f365) CACHE_TYPE('d10) START_TIME(3288000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23504000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100002) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITEEVICT) ID('h1) SECURE('d1) ADDR('h82bd33e6) CACHE_TYPE('d11) START_TIME(3296000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_120__tb_mq2_sq2__rx_strobe_loc_10/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23660000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100000) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READONCECLEANINVALID) ID('h6) SECURE('d1) ADDR('h4ce7500f93ae) CACHE_TYPE('d15) START_TIME(2608000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23650000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100013) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READCLEAN) ID('hf) SECURE('d1) ADDR('hb8825b03d72b) CACHE_TYPE('d7) START_TIME(3592000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_123__tb_mq2_sq2__rx_strobe_loc_49/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 7304000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 4d2b1e73 && s_xact: 4d3b1e73
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 7304000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: f70a9fa0 && s_xact: f71a9fa0
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 7304000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: c14dfedf && s_xact: c15dfedf
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 7304000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: a8e2f930 && s_xact: a8f2f930
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3694000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: ca4d3cfe && s_xact: ca5d3cfe
regression/test_127__tb_mq2_sq2__rx_strobe_loc_87/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23484000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100000) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READSHARED) ID('h5) SECURE('d1) ADDR('h395514c7) CACHE_TYPE('d1) START_TIME(2608000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23486000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(DVMMESSAGE) ID('h3) SECURE('d0) ADDR('h44d962c0) CACHE_TYPE('d6) START_TIME(3458000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_129__tb_mq2_sq2__rx_strobe_loc_109/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 5
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3648000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 98c489f736e633455120786ae3d339a80d6cc36219329e48d5eeb6c3b4af75a427cca0d1aca5c9f78da5896668d80291016e91a55f832964fbb2c58e916a8514 && s_xact: 98c489f736e633455120786ae3d339a80d6cc36219329e48d5eeb6c3b4af75a427cca0d1aca5c9f78da5896668d80291016e99a55f832964fbb2c58e916a8514
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4366000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 785d5b5c1a47988559ca2207337abc63dc17117f85f163580340fcc0617fa806d5f0f841e773604807e93d7eff9c5c538e2552928562197839391d33b5f7ea29 && s_xact: 785d5b5c1a47988559ca2207377abc63dc17117f85f163580340fcc0617fa806d5f0f841e773604807e93d7eff9c5c538e2552928562197839391d33b5f7ea29
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4726000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 8a97a092d7ce876dcef287cd702b304e575c60fe4410fbf0521e40e25d0938c3ee1c2ff33fe36ef0ad4ab002e7319c415b52710f943efcc06802b849b3306d95 && s_xact: 8a97a092d7ce876dcef287cd742b304e575c60fe4410fbf0521e40e25d0938c3ee1c2ff33fe36ef0ad4ab002e7319c415b52790f943efcc06802b849b3306d95
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4908000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: d39f9b827a8908f248d3a8cea0f58b9b4190c95e40cb6790b8f1e471a85505f50ba26a9d192a7e677d54043b1a9aded36c5e602ef0b1df8968f1022451b03a49 && s_xact: d39f9b827a8908f248d3a8cea4f58b9b4190c95e40cb6790b8f1e471a85505f50ba26a9d192a7e677d54043b1a9aded36c5e602ef0b1df8968f1022451b03a49
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_directed_test_m2s2.log:UVM_ERROR : 5
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_131__tb_mq2_sq2__rx_strobe_loc_127/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 1
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3738000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 7d952ced10adc33ac2e326e557497ddaee2af0c227e8eff12ab006ad8a10bcf6177d4dcf5ddeea6eec9714cc05e0dbc6a641573ddd69bff753cfb15efa554bcf && s_xact: 7d952ced10adc33ac2e326e557497ddaee2af0c227e8eff12ab006ad8a10bcf6177d4dcf5ddeea6eec9714cc0de0dbc6a641573ddd69bff753cfb15efa554bcf
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3940000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: ae9d286440b93f28df433977d2628d34e19a6ff6aa9362c12eea67f1c3db63690ce434d15ff4c447ad0a8bacc245273839200f32ff49f4247f9cd09bcd2a84bd && s_xact: ae9d286440b93f28df433977d2628d34e19a6ff6aa9362c12eea67f1c3db63690ce434d15ff4c447ad0a8bacca45273839200f32ff49f4247f9cd09bcd2a84bd
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4144000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: c77839d3db94143b4d0ddfdcb68ad4704c6b3ad1caa09eb1dde0ce6c0f6dab9e0df4ae6ed77f69ffc48b9101b48e395e1af599bb2b7d0dbd701f4ae6aeed5720 && s_xact: c77839d3db94147b4d0ddfdcb68ad4704c6b3ad1caa09eb1dde0ce6c0f6dab9e0df4ae6ed77f69ffc48b9101b48e395e1af599bb2b7d0dbd701f4ae6aeed5720
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4354000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 4a7516a2be483f2ef47eac92a2466ef80046ee2cdf5a994553ca5289bf66e0214bbf9617bf315810fd6086fff3f0acb944cfc66d2baf23012533224357f86170 && s_xact: 4a7516a2be483f6ef47eac92a2466ef80046ee2cdf5a994553ca5289bf66e0214bbf9617bf315810fd6086fff3f0acb944cfc66d2baf23012533224357f86170
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4566000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 8421809f8627de20f6313c78a10f422fc86e60f69148400065b685f08f90607f1a6265b8f98c015a60d9c5ab42e73e96471c06f6eb27892f1568c3a119e5241d && s_xact: 8421809f8627de60f6313c78a10f422fc86e60f69148400065b685f08f90607f1a6265b8f98c015a60d9c5ab42e73e96471c06f6eb27892f1568c3a119e5241d
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_directed_test_m2s2.log:UVM_ERROR : 5
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4418000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: ecb27df0edb4a5947a55370f3aab108f72b37a326ac3e0738ecc8086616f0affb980535aaac02f14cca6abff34cd07c658e741e85646cce8ff1eccde474053f4 && s_xact: ecb27df0edb4a5d47a55370f3aab108f72b37a326ac3e0738ecc8086616f0affb980535aaac02f14cca6abff34cd07c658e741e85646cce8ff1eccde474053f4
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4418000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: e03a1bedc21a6713d81193c7b6f155e8f079da2e974b73a4c8da3830cb1b0b9ad47a6cf2edc562b3e6da165e600fa9b334703a40451eef889d32c21abe4fa512 && s_xact: e03a1bedc21a6753d81193c7b6f155e8f079da2e974b73a4c8da3830cb1b0b9ad47a6cf2edc562b3e6da165e680fa9b334703a40451eef889d32c21abe4fa512
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4418000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 80c97d701e79f030e469a36ae79597fd381c322e75edc95bb90dd94d68bb6add7d5e28b3fc9ec801c4c992260006529939721a80dc9cbb91cede6f8c9e66487f && s_xact: 80c97d701e79f030e469a36ae79597fd381c322e75edc95bb90dd94d68bb6add7d5e28b3fc9ec801c4c992260806529939721a80dc9cbb91cede6f8c9e66487f
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4418000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: f05cceb97e51f89cfdd3eee974ff41f08d18aad73e3db3ba790c6ca55dc0e4770517c0da4bd3fe25f285fc06b610ce4b9c5767c514b1616dcbff0f6c70006711 && s_xact: f05cceb97e51f8dcfdd3eee974ff41f08d18aad73e3db3ba790c6ca55dc0e4770517c0da4bd3fe25f285fc06b610ce4b9c5767c514b1616dcbff0f6c70006711
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3622000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: 32ad2546bb7c079d20b5e96c52cc63c250bcfa800bba2e76569f8c546de4fb6790c0c709b9360ec3f9cc5f4cc4028d86c3fe7d21ae1d2edc554d05d503c5c338 && s_xact: 32ad2546bb7c07dd20b5e96c52cc63c250bcfa800bba2e76569f8c546de4fb6790c0c709b9360ec3f9cc5f4ccc028d86c3fe7d21ae1d2edc554d05d503c5c338
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 3622000: uvm_test_top.aximm_scb [compare_transaction_field] Data mismatch: m_xact: b06e3fabd60f2f87ea917fe1890f4d9303dcd0de2cb1cddf6c95e27eda4f2abc77ba412b4ce4909d2cb4661b665c3fc8eab100139e7f8775119d588d4f4267b8 && s_xact: b06e3fabd60f2fc7ea917fe1890f4d9303dcd0de2cb1cddf6c95e27eda4f2abc77ba412b4ce4909d2cb4661b6e5c3fc8eab100139e7f8775119d588d4f4267b8
regression/test_132__tb_mq2_sq2__rx_strobe_loc_136/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
Binary file regression/test_133__tb_mq2_sq2__rx_strobe_loc_142/logs/sim_directed_test_m2s2.log matches
regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23816000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100002) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITELINEUNIQUE) ID('hd) SECURE('d0) ADDR('hedb614d292c2) CACHE_TYPE('d0) START_TIME(3580000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23810000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100007) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(DVMMESSAGE) ID('hb) SECURE('d0) ADDR('hc3e179a25b34) CACHE_TYPE('d14) START_TIME(3770000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_135__tb_mq2_sq2__rx_strobe_loc_164/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5838000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d1) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h1) SECURE('d1) ADDR('h1bf4d0ff) CACHE_TYPE('d0) START_TIME(3488000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1478) @ 3696000: uvm_test_top.aximm_scb [compare_transaction_field] Burst length mismatch: m_xact: 2 && s_xact: 1
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1480) @ 3696000: uvm_test_top.aximm_scb [compare_transaction_field] Address mismatch: m_xact: ae07bc2a && s_xact: 8b7360d0
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/env/aximm_scoreboard.sv(1484) @ 3696000: uvm_test_top.aximm_scb [compare_transaction_field] burst_size mismatch: m_xact: BURST_SIZE_256BIT && s_xact: BURST_SIZE_8BIT
regression/test_136__tb_mq2_sq2__rx_strobe_loc_179/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5810000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('ha) SECURE('d1) ADDR('hb5f3996e56d8) CACHE_TYPE('d0) START_TIME(3582000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3926000: reporter [is_valid] Invalid wstrb[0] of 0xabf64000 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3926000: reporter [is_valid] Invalid wstrb[1] of 0x1746f982 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3926000: reporter [is_valid] Invalid wstrb[2] of 0x7320be61 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3926000: reporter [is_valid] Invalid wstrb[3] of 0x8d91268e provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3926000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:valid_write_strobe_check] Description: Monitor Check that valid Write Strobes are driven for each data beat!
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5812000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d7) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('hd) SECURE('d1) ADDR('hbe98b3ac5584) CACHE_TYPE('d0) START_TIME(3612000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : 4
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 1
regression/test_137__tb_mq2_sq2__rx_strobe_loc_180/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23538000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100000) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READSHARED) ID('h5) SECURE('d1) ADDR('h6e7065768f1) CACHE_TYPE('d2) START_TIME(2608000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23528000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100009) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(MAKEINVALID) ID('hf) SECURE('d1) ADDR('h176bfdd8bc2b) CACHE_TYPE('d10) START_TIME(3506000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_138__tb_mq2_sq2__rx_strobe_loc_196/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23828000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100001) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READCLEAN) ID('h5) SECURE('d1) ADDR('h1081dca091c6) CACHE_TYPE('d6) START_TIME(3574000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23816000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(DVMMESSAGE) ID('h4) SECURE('d1) ADDR('h54ea40cfc4a0) CACHE_TYPE('d6) START_TIME(3626000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_139__tb_mq2_sq2__rx_strobe_loc_208/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR : 5
regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_143__tb_mq2_sq2__rx_strobe_loc_240/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5852000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d0) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h8) SECURE('d1) ADDR('hacf3c842) CACHE_TYPE('d0) START_TIME(3644000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23902000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(CLEANINVALID) ID('h6) SECURE('d0) ADDR('ha0de7c53) CACHE_TYPE('d1) START_TIME(3748000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_145__tb_mq2_sq2__rx_strobe_loc_266/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
Binary file regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_directed_test_m2s2.log matches
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3480000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:awaddr_4k_boundary_cross_active_check] Description: Monitor Check that a write burst cannot cross a 4K boundary! - addr = 'h9fb18778d6f8. burst_length = 'd159. burst_size = BURST_SIZE_128BIT
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3498000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:awaddr_4k_boundary_cross_active_check] Description: Monitor Check that a write burst cannot cross a 4K boundary! - addr = 'h41ed3b483703. burst_length = 'd84. burst_size = BURST_SIZE_256BIT
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3694000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:awaddr_4k_boundary_cross_active_check] Description: Monitor Check that a write burst cannot cross a 4K boundary! - addr = 'h29507ccb2ab5. burst_length = 'd46. burst_size = BURST_SIZE_256BIT
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3870000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:wlast_asserted_for_last_write_data_beat] Description: Monitor Check that WLAST is asserted for last beat of write data!
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3870000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:wdata_awlen_match_for_corresponding_awaddr_check] Description: Monitor Check that the number of write data items matches AWLEN for the corresponding address!
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23606000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITEBARRIER) ID('h8) SECURE('d0) ADDR('h7859f6dee81) CACHE_TYPE('d6) START_TIME(3514000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_147__tb_mq2_sq2__rx_strobe_loc_281/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23514000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100002) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(MAKEINVALID) ID('h1) SECURE('d0) ADDR('hede20609) CACHE_TYPE('d14) START_TIME(3294000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23506000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READBARRIER) ID('h3) SECURE('d1) ADDR('h365eca59) CACHE_TYPE('d14) START_TIME(3346000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_148__tb_mq2_sq2__rx_strobe_loc_291/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 6120000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d1) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h5) SECURE('d1) ADDR('h9810a2ca54d5) CACHE_TYPE('d0) START_TIME(3770000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 6114000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d9) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h8) SECURE('d1) ADDR('h4f5c314144f3) CACHE_TYPE('d0) START_TIME(3822000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_149__tb_mq2_sq2__rx_strobe_loc_301/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23664000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100001) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READONCE) ID('hd) SECURE('d0) ADDR('h5f0e4439) CACHE_TYPE('d10) START_TIME(3336000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23632000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100009) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITENOSNOOP) ID('h2) SECURE('d0) ADDR('h3b1c41ee) CACHE_TYPE('d6) START_TIME(3626000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_153__tb_mq2_sq2__rx_user_strobe_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(254) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set 50002000
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3602000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:awaddr_4k_boundary_cross_active_check] Description: Monitor Check that a write burst cannot cross a 4K boundary! - addr = 'hb0c00dd5. burst_length = 'd51. burst_size = BURST_SIZE_128BIT
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3606000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:wlast_asserted_for_last_write_data_beat] Description: Monitor Check that WLAST is asserted for last beat of write data!
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3606000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:wdata_awlen_match_for_corresponding_awaddr_check] Description: Monitor Check that the number of write data items matches AWLEN for the corresponding address!
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3658000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:awaddr_4k_boundary_cross_active_check] Description: Monitor Check that a write burst cannot cross a 4K boundary! - addr = 'h49e3fad6. burst_length = 'd213. burst_size = BURST_SIZE_128BIT
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 3674000: uvm_test_top.axi_env.axi_system_env.master[0] [sample()] Saw bvalid assertion for id 'h2. But, no corresponding transaction found
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_random_wr_rd_test_m2s2.log:UVM_ERROR : 5
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 23614000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100011) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READONCECLEANINVALID) ID('hf) SECURE('d0) ADDR('h82b9c67f) CACHE_TYPE('d3) START_TIME(3584000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_159__tb_mq2_sq2__tx_marker_loc_78/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5720000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d2) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('ha) SECURE('d1) ADDR('hbb88e6d89aaf) CACHE_TYPE('d0) START_TIME(3440000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3702000: reporter [is_valid] Invalid wstrb[0] of 0x8000000 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3702000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:valid_write_strobe_check] Description: Monitor Check that valid Write Strobes are driven for each data beat!
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5674000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d5) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('h7) SECURE('d1) ADDR('hc64f4f079ec3) CACHE_TYPE('d0) START_TIME(3456000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : 1
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 1
regression/test_175__tb_mq2_sq2__tx_strobe_loc_104/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_directed_test_m2s2.log:UVM_ERROR .//0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv(238) @ 50002000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set 50002000
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5828000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d1) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('hd) SECURE('d1) ADDR('h5149c96fac1f) CACHE_TYPE('d0) START_TIME(3536000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_random_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL .//svt_axi_base_slave_common.svp(9022) @ 5794000: uvm_test_top.axi_env.axi_system_env.slave[0] [wait_for_rready] {OBJECT_NUM('d6) PORT_ID('d0) PORT_NAME(slave[0]) TYPE(READ) COHERENT_XACT_TYPE(READNOSNOOP) ID('hf) SECURE('d1) ADDR('h6a0a17cd147) CACHE_TYPE('d0) START_TIME(3560000)} Timed out waiting for rready after rvalid assertion. Timeout = 'd1000 clock cycles Watchdog Timer = svt_axi_system_configuration::rready_watchdog_timeout,If the current timer value 'd 1000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::rready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::rready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_200__tb_mq2_sq2__tx_user_strobe_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1

johna-eximiusdesign · Answer 2 · Wed Dec 22 2021 23:34:58 GMT+0800 (China Standard Time)

We don't see any UVM_WARNING, UVM_FATAL or UVM_ERROR in our regressions. I've uploaded the logs from our Dec 10 AXIMM run to the Intel Sharepoint (From Eximius -> regression_results -> regression_aximm_norm_dec10.tgz) which should match the drop you got on the 14th. So I'm not sure what is wrong with your setup.

You may want to revert to the same version of the Synopsys VIP we used as that is at least one difference.

johna-eximiusdesign · Answer 3 · Wed Dec 22 2021 23:41:57 GMT+0800 (China Standard Time)

Additionally, if you would like to provide 3 or 4 of your failing sailrocks configurations, we can re-run the simulations in our environment and see if they pass.

nij-intel · Answer 4 · Thu Dec 23 2021 00:50:02 GMT+0800 (China Standard Time)

Sent these log files with sailrock.cfg

regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_directed_4kboundary_test_m2s2.log
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_directed_test_m2s2.log
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_random_wr_rd_test_m2s2.log
regression/test_000__tb_mf2_sf2__addr_width_32/logs/sim_reorder_wr_rd_test_m2s2.log
regression/test_000__tb_mf2_sf2__addr_width_32/sailrock_cfg.txt
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_directed_4kboundary_test_m2s2.log
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_directed_test_m2s2.log
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_random_wr_rd_test_m2s2.log
regression/test_040__tb_mh2_sh2__data_width_256/logs/sim_reorder_wr_rd_test_m2s2.log
regression/test_040__tb_mh2_sh2__data_width_256/sailrock_cfg.txt
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/sailrock_cfg.txt
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_directed_4kboundary_test_m2s2.log
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_directed_test_m2s2.log
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_random_wr_rd_test_m2s2.log
regression/test_047__tb_mh2_sh2__rx_marker_loc_79/logs/sim_reorder_wr_rd_test_m2s2.log

johna-eximiusdesign · Answer 5 · Thu Dec 23 2021 02:01:57 GMT+0800 (China Standard Time)

Re-ran the three provided configurations through the regression suite. All three passed without any UVM_ERROR, UVM_FATAL or UVM_WARNING messages. Sent logs showing the results for both compile logs and simulation logs.

johna-eximiusdesign · Answer 6 · Thu Dec 23 2021 03:12:24 GMT+0800 (China Standard Time)

FYI, the failing configurations provided were re-run in repositories from:

Dec 14 drop to Intel (0.9.1)
latest repo (circa Dec 22, soon to be 0.9.2)

Both had the same result. All regression tests passed, no UVM_WARNINGs, UVM_FATALs or UVM_ERRORs.

johna-eximiusdesign · Answer 7 · Wed Jan 05 2022 03:05:34 GMT+0800 (China Standard Time)

All known test failures have been fixed in 0.9.3 with the single exception of the WSTRB failures which are a Synopsys bug. Synopsys says this should be fixed in the next release of VIP. Other than those failures, we've run 3 full AXIMM, AXILITE and AXIST regression suites with no other errors.

The VIP failure in AXIMM arises because the Slave VIP objects to receiving a W beat with WSTRB being all 0, even though that is what the Master VIP is issuing (and appears legal per the Spec). The DUT is doing as requested and passing the command from master to slave, so this is a Synopsys inconsistency on what is legal. Synopsys AE says it is a bug and it should be fixed in the next release. Until then, we've seen a total of 3 errors across 3 full regressions (~2200 tests) so these are reasonably rate and can be safely ignored. An example of the failure are below:

UVM_WARNING /g/tools/synopsys/VIP_SoC_Library/vip/svt/amba_svt/R-2020.12/sverilog/src/vcs/svt_axi_transaction.svp(14793) @ 3525500: reporter [is_valid] Invalid wstrb[0] of 0xdf830000 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
UVM_ERROR /g/tools/synopsys/VIP_SoC_Library/vip/svt/common/S-2021.09/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3525500: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:valid_write_strobe_check] Description: Monitor Check that valid Write Strobes are driven for each data beat!

nij-intel · Answer 8 · Wed Jan 05 2022 08:35:22 GMT+0800 (China Standard Time)

Half of my tests from 0.9.3 completed, I am seeing couple of issues:

Value of wstrb exceeded what can be supported by burst size
wait_for_wready timeout
burst length mismatch: m_xact: 1 && s_xact: 4

regression/test_042__tb_mh2_sh2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/sverilog/src/vcs/svt_axi_transaction.svp(16526) @ 3519000: reporter [is_valid] Invalid wstrb[0] of 0x9880000000000000 provided, must be <= 0x1 based on port_cfg.wysiwyg_enable('b0), xact_type(WRITE) and burst_size(BURST_SIZE_8BIT). Value of wstrb exceeds what can be supported by burst_size
regression/test_042__tb_mh2_sh2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/common/S-2021.06/sverilog/src/vcs/svt_err_check_stats.svp(583) @ 3519000: uvm_test_top.axi_env.axi_system_env.slave[0].monitor [register_fail:AMBA:AXI3:valid_write_strobe_check] Description: Monitor Check that valid Write Strobes are driven for each data beat!
regression/test_042__tb_mh2_sh2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_WARNING : 1
regression/test_042__tb_mh2_sh2__rx_dbi_0/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 1
regression/test_051__tb_mh2_sh2__rx_perst_strobe_1/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(253) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set: 50001000
regression/test_051__tb_mh2_sh2__rx_perst_strobe_1/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(253) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set: 50001000
regression/test_051__tb_mh2_sh2__rx_perst_strobe_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13517000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100007) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READNOTSHAREDDIRTY) ID('h6) SECURE('d0) ADDR('h3920e133) CACHE_TYPE('d15) START_TIME(3499000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_051__tb_mh2_sh2__rx_perst_strobe_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_052__tb_mh2_sh2__rx_strobe_loc_2/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(253) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set: 50001000
regression/test_052__tb_mh2_sh2__rx_strobe_loc_2/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(253) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_slave.rx_online is not set: 50001000
regression/test_055__tb_mh2_sh2__rx_strobe_loc_34/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_055__tb_mh2_sh2__rx_strobe_loc_34/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_055__tb_mh2_sh2__rx_strobe_loc_34/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13414000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100005) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITECLEAN) ID('h7) SECURE('d0) ADDR('h174132ab) CACHE_TYPE('d6) START_TIME(3387000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_055__tb_mh2_sh2__rx_strobe_loc_34/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_061__tb_mh2_sh2__rx_strobe_loc_97/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_082__tb_mh2_sh2__tx_strobe_loc_6/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_093__tb_mh2_sh2__tx_strobe_loc_114/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_093__tb_mh2_sh2__tx_strobe_loc_114/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_093__tb_mh2_sh2__tx_strobe_loc_114/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13385000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100006) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(WRITECLEAN) ID('h7) SECURE('d0) ADDR('h6c307b5c4512) CACHE_TYPE('d1) START_TIME(3357000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_093__tb_mh2_sh2__tx_strobe_loc_114/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_096__tb_mh2_sh2__tx_strobe_loc_143/logs/sim_directed_4kboundary_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_096__tb_mh2_sh2__tx_strobe_loc_143/logs/sim_directed_reset_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_096__tb_mh2_sh2__tx_strobe_loc_143/logs/sim_directed_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/tb/aximm_top_tb.sv(235) @ 50001000: reporter [aximm_top_tb] aximm_DUT_wrapper.aximm_ll_msr.rx_online is not set: 50001000
regression/test_096__tb_mh2_sh2__tx_strobe_loc_143/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL /nfs/sc/disks/psg_extsynopsysvip_1/vip_common/vip_S-2021.06D/vip/svt/amba_svt/S-2021.06/axi_master_svt/sverilog/src/vcs/svt_axi_base_master_common.svp(9707) @ 13502000: uvm_test_top.axi_env.axi_system_env.master[0] [wait_for_wready] {OBJECT_NUM('d100007) PORT_ID('d0) PORT_NAME() TYPE(WRITE) COHERENT_XACT_TYPE(READNOSNOOP) ID('h5) SECURE('d1) ADDR('hbd92f1a45380) CACHE_TYPE('d6) START_TIME(3471000)} Timed out waiting for wready after wvalid assertion. Timeout = 'd10000 clock cyclesWatchdog Timer = svt_axi_system_configuration::wready_watchdog_timeout, If the current timer value 'd 10000 clock cycles is not sufficient for the DUT to respond, increase the timeout variable svt_axi_system_configuration::wready_watchdog_timeout to match the maximum expected delay from DUT. To disable the timer, set svt_axi_system_configuration::wready_watchdog_timeout to zero. In this case, the VIP will indefinitely wait for the signal from DUT. If the signal is never received, it may result in simulation hang. This timeout might result in protocol violation errors as VIP assumes signal is not going to be recieved and proceeds with next beat, But if DUT sends it after some delay it might result in all sorts of protocol voilations
regression/test_096__tb_mh2_sh2__tx_strobe_loc_143/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_FATAL : 1
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/env/aximm_scoreboard.sv(1492) @ 4234000: uvm_test_top.aximm_scb [compare_transaction_field] Burst length mismatch: m_xact: 1 && s_xact: 4
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/env/aximm_scoreboard.sv(1494) @ 4234000: uvm_test_top.aximm_scb [compare_transaction_field] Address mismatch: m_xact: 45c301d90e8d && s_xact: 24aaaeb78300
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/env/aximm_scoreboard.sv(1496) @ 4234000: uvm_test_top.aximm_scb [compare_transaction_field] ID mismatch: m_xact: 6 && s_xact: 2
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/env/aximm_scoreboard.sv(1498) @ 4234000: uvm_test_top.aximm_scb [compare_transaction_field] burst_size mismatch: m_xact: BURST_SIZE_8BIT && s_xact: BURST_SIZE_512BIT
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR /nfs/sc/disks/swuser_work_ndoraira/csprs/eximius/0.9.3/llink/dv/aximm/env/aximm_scoreboard.sv(1500) @ 4234000: uvm_test_top.aximm_scb [compare_transaction_field] burst_type mismatch: m_xact: INCR && s_xact: WRAP
regression/test_197__tb_mq2_sq2__tx_user_marker_1/logs/sim_reorder_wr_rd_test_m2s2.log:UVM_ERROR : 5

Commands to reproduce:

0.9.3/llink/dv/aximm/regression/test_042__tb_mh2_sh2__rx_dbi_0/./simv +UVM_TESTNAME=reorder_wr_rd_test +ntb_random_seed=38509985 +UVM_VERBOSITY=UVM_NONE +UVM_MAX_QUIT_COUNT=5 +AIB_IF_COUNT=1 +AIB_CONFIG_DIR=./ +AIB_MASTER_CONFIG_FILE=./master_0_config_aib.dat +AIB_SLAVE_CONFIG_FILE=./slave_0_config_aib.dat -l ./logs/sim_reorder_wr_rd_test_m2s2.log -cm line+cond+tgl+fsm+branch+assert +AXI3 +nospecify +WAVES_OFF
/0.9.3/llink/dv/aximm/regression/test_051__tb_mh2_sh2__rx_perst_strobe_1/./simv +UVM_TESTNAME=reorder_wr_rd_test +ntb_random_seed=52069441 +UVM_VERBOSITY=UVM_NONE +UVM_MAX_QUIT_COUNT=5 +AIB_IF_COUNT=1 +AIB_CONFIG_DIR=./ +AIB_MASTER_CONFIG_FILE=./master_0_config_aib.dat +AIB_SLAVE_CONFIG_FILE=./slave_0_config_aib.dat -l ./logs/sim_reorder_wr_rd_test_m2s2.log -cm line+cond+tgl+fsm+branch+assert +AXI3 +nospecify +WAVES_OFF
/0.9.3/llink/dv/aximm/regression/test_052__tb_mh2_sh2__rx_strobe_loc_2/./simv +UVM_TESTNAME=directed_test +ntb_random_seed=57409451 +UVM_VERBOSITY=UVM_NONE +UVM_MAX_QUIT_COUNT=5 +AIB_IF_COUNT=1 +AIB_CONFIG_DIR=./ +AIB_MASTER_CONFIG_FILE=./master_0_config_aib.dat +AIB_SLAVE_CONFIG_FILE=./slave_0_config_aib.dat -l ./logs/sim_directed_test_m2s2.log -cm line+cond+tgl+fsm+branch+assert +nospecify +WAVES_OFF
0.9.3/llink/dv/aximm/regression/test_197__tb_mq2_sq2__tx_user_marker_1/./simv +UVM_TESTNAME=reorder_wr_rd_test +ntb_random_seed=44128549 +UVM_VERBOSITY=UVM_NONE +UVM_MAX_QUIT_COUNT=5 +AIB_IF_COUNT=1 +AIB_CONFIG_DIR=./ +AIB_MASTER_CONFIG_FILE=./master_0_config_aib.dat +AIB_SLAVE_CONFIG_FILE=./slave_0_config_aib.dat -l ./logs/sim_reorder_wr_rd_test_m2s2.log -cm line+cond+tgl+fsm+branch+assert +AXI3 +nospecify +WAVES_OFF

nij-intel · Answer 9 · Wed Jan 05 2022 10:01:15 GMT+0800 (China Standard Time)

Completed 0.9.3 AXIMM with these results:

Total Config: 261
Config Errors: 15
Total Tests: 1044
Test Errors: 48
Tue Jan 4 17:49:32 PST 2022

There are runs with failures and runs that did not complete

:../dv/aximm:696> grep "with error" regression_results.txt
grep "with error" regression_results.txt
ERROR: regression/test_042__tb_mh2_sh2__rx_dbi_0 reorder_wr_rd_test completed with errors.
ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 reorder_wr_rd_test completed with errors.
ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 reorder_wr_rd_test completed with errors.
ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 reorder_wr_rd_test completed with errors.
ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 reorder_wr_rd_test completed with errors.
ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 reorder_wr_rd_test completed with errors.
ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 reorder_wr_rd_test completed with errors.
ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 reorder_wr_rd_test completed with errors.
ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 reorder_wr_rd_test completed with errors.
ERROR: regression/test_197__tb_mq2_sq2__tx_user_marker_1 reorder_wr_rd_test completed with errors.
:../dv/aximm:697> grep "did not fi" regression_results.txt
grep "did not fi" regression_results.txt
ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 directed_test did not finish.
ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 directed_4kboundary_test did not finish.
ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 random_wr_rd_test did not finish.
ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 directed_test did not finish.
ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 directed_4kboundary_test did not finish.
ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 random_wr_rd_test did not finish.
ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 directed_test did not finish.
ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 directed_4kboundary_test did not finish.
ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 random_wr_rd_test did not finish.
ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 directed_test did not finish.
ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 directed_4kboundary_test did not finish.
ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 random_wr_rd_test did not finish.
ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 directed_test did not finish.
ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 directed_4kboundary_test did not finish.
ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 directed_test did not finish.
ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 directed_4kboundary_test did not finish.
ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 random_wr_rd_test did not finish.
ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 directed_test did not finish.
ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 directed_4kboundary_test did not finish.
ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 random_wr_rd_test did not finish.
ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 directed_test did not finish.
ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 directed_4kboundary_test did not finish.
ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 random_wr_rd_test did not finish.
ERROR: regression/test_182__tb_mq2_sq2__tx_strobe_loc_175 random_wr_rd_test did not finish.
ERROR: regression/test_258__tb_mh2.1_sh1__tx_user_marker_1 random_wr_rd_test did not finish.

I will send the zip of these tests over for further analysis

johna-eximiusdesign · Answer 10 · Wed Jan 05 2022 11:54:40 GMT+0800 (China Standard Time)

For the first set of 4 that you gave details on: test_042 is the WSTRB issue that has been described before and is the Synopsys VIP issue These tests: test_052 test_055 test_061 test_082 test_093 test_096 All seem to have the same basic issue, namely that the system did not go online in the expected time. I suspect the wready timeout is a related side effect. Online comes from the AIB and CA. We don't see this on our side, so I'd ask if you are using the same AIB as we are using (i.e. from the github repo or if you have a local branch or anything)? The best approach here is to pick one (say test_051) and generate waves on it. Lets debug this tomorrow during our 1-on-1. Test_197 similarly looks odd and I cannot explain the failure, but it seems like the scoreboard is expecting a completely different AXI transaction than what was delivered by the DUT. The next step is to look at the waves and see what was sent into the DUT, and if that is the same, then we'll need to look at the scoreboard for why we got this failure. To regenerate the waves for test_051 or test_197: 1. cd into test_051 or test_197 2. run make comp_all MODE=m2s2 3. run (same as above but with +WAVE_OFF removed so we generate waves). ./simv +UVM_TESTNAME=reorder_wr_rd_test +ntb_random_seed=52069441 +UVM_VERBOSITY=UVM_NONE +UVM_MAX_QUIT_COUNT=5 +AIB_IF_COUNT=1 +AIB_CONFIG_DIR=./ +AIB_MASTER_CONFIG_FILE=./master_0_config_aib.dat +AIB_SLAVE_CONFIG_FILE=./slave_0_config_aib.dat -l ./logs/sim_reorder_wr_rd_test_m2s2.log -cm line+cond+tgl+fsm+branch+assert +AXI3 +nospecify Additionally, if you will send me those 2 sailrocks, we can try to reproduce locally. But as I've said, the same seed doesn't seem to produce the same results on different companies' systems. But if you have your waves and I have mine, we can confirm that. John

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On Tue, Jan 4, 2022 at 8:01 PM nij-intel ***@***.***> wrote: Completed 0.9.3 AXIMM with these results: Total Config: 261 Config Errors: 15 Total Tests: 1044 Test Errors: 48 Tue Jan 4 17:49:32 PST 2022 There are runs with failures and runs that did not complete :../dv/aximm:696> grep "with error" regression_results.txt grep "with error" regression_results.txt ERROR: regression/test_042__tb_mh2_sh2__rx_dbi_0 reorder_wr_rd_test completed with errors. ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 reorder_wr_rd_test completed with errors. ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 reorder_wr_rd_test completed with errors. ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 reorder_wr_rd_test completed with errors. ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 reorder_wr_rd_test completed with errors. ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 reorder_wr_rd_test completed with errors. ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 reorder_wr_rd_test completed with errors. ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 reorder_wr_rd_test completed with errors. ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 reorder_wr_rd_test completed with errors. ERROR: regression/test_197__tb_mq2_sq2__tx_user_marker_1 reorder_wr_rd_test completed with errors. :../dv/aximm:697> grep "did not fi" regression_results.txt grep "did not fi" regression_results.txt ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 directed_test did not finish. ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 directed_4kboundary_test did not finish. ERROR: regression/test_051__tb_mh2_sh2__rx_perst_strobe_1 random_wr_rd_test did not finish. ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 directed_test did not finish. ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 directed_4kboundary_test did not finish. ERROR: regression/test_052__tb_mh2_sh2__rx_strobe_loc_2 random_wr_rd_test did not finish. ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 directed_test did not finish. ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 directed_4kboundary_test did not finish. ERROR: regression/test_055__tb_mh2_sh2__rx_strobe_loc_34 random_wr_rd_test did not finish. ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 directed_test did not finish. ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 directed_4kboundary_test did not finish. ERROR: regression/test_061__tb_mh2_sh2__rx_strobe_loc_97 random_wr_rd_test did not finish. ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 directed_test did not finish. ERROR: regression/test_077__tb_mh2_sh2__tx_marker_loc_79 directed_4kboundary_test did not finish. ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 directed_test did not finish. ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 directed_4kboundary_test did not finish. ERROR: regression/test_082__tb_mh2_sh2__tx_strobe_loc_6 random_wr_rd_test did not finish. ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 directed_test did not finish. ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 directed_4kboundary_test did not finish. ERROR: regression/test_093__tb_mh2_sh2__tx_strobe_loc_114 random_wr_rd_test did not finish. ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 directed_test did not finish. ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 directed_4kboundary_test did not finish. ERROR: regression/test_096__tb_mh2_sh2__tx_strobe_loc_143 random_wr_rd_test did not finish. ERROR: regression/test_182__tb_mq2_sq2__tx_strobe_loc_175 random_wr_rd_test did not finish. ERROR: regression/test_258__tb_mh2.1_sh1__tx_user_marker_1 random_wr_rd_test did not finish. I will send the zip of these tests over for further analysis — Reply to this email directly, view it on GitHub <#58 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AUYPV2MKO3APKD56LESBFWDUUOQ7LANCNFSM5KPBGHRQ> . Triage notifications on the go with GitHub Mobile for iOS <https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675> or Android <https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub>. You are receiving this because you were assigned.Message ID: ***@***.***>

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nij-intel · Answer 11 · Thu Jan 20 2022 06:21:34 GMT+0800 (China Standard Time)

Once I check WSTRB==0 issue on 0.9.5 I will close this.

nij-intel · Answer 12 · Sat Jan 22 2022 06:58:05 GMT+0800 (China Standard Time)

fixed in 0.9.5