AXI4 warnings clean up
nij-intel opened this issue · comments
Just starting to reproduce regression here noticed these warnings:
Warning-[MATN] More arguments than needed
./0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv, 230
"$time"
More arguments than format specifiers in format string. Expecting 0 only.
Warning-[MATN] More arguments than needed
./0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv, 238
"$time"
More arguments than format specifiers in format string. Expecting 0 only.
Warning-[MATN] More arguments than needed
./0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv, 246
"$time"
More arguments than format specifiers in format string. Expecting 0 only.
Warning-[MATN] More arguments than needed
./0.9.1/llink/dv/aximm/tb/aximm_top_tb.sv, 254
"$time"
More arguments than format specifiers in format string. Expecting 0 only.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 261
"axi_mm_master_top aximm_ll_msr( .clk_wr (aximm_top_tb.msr_wr_clk), .rst_wr_n (axi_if.master_if[0].aresetn), .tx_online (llink_m_tx_online), .rx_online (llink_m_tx_online), .init_ar_credit (8'b0), .init_aw_credit (8'b0), .init_w_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_m1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_m1.data_out_f[(80 - 1):0]), .user_arid (axi_if.master_if[0].arid), .user_arsize (axi_if.master_if[0].arsize), .user_arlen (axi_if.master_if[0].arlen), .user_arburst (axi_if.master_if[0].arburst), .user_araddr (axi_if.master_if[0].araddr), .user_arvalid (axi_if.master_if[0].arvalid), .user_arready (axi_if.master_if[0].arready), .user_awid (axi_if.master_if[0].awid), .user_awsize (axi_if.master_if[0].awsize), .user_aw ... "
The following 32-bit expression is connected to 16-bit port "delay_x_value"
of module "axi_mm_master_top", instance "aximm_ll_msr".
Expression: MASTER_DELAY_X_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_master_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 261
"axi_mm_master_top aximm_ll_msr( .clk_wr (aximm_top_tb.msr_wr_clk), .rst_wr_n (axi_if.master_if[0].aresetn), .tx_online (llink_m_tx_online), .rx_online (llink_m_tx_online), .init_ar_credit (8'b0), .init_aw_credit (8'b0), .init_w_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_m1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_m1.data_out_f[(80 - 1):0]), .user_arid (axi_if.master_if[0].arid), .user_arsize (axi_if.master_if[0].arsize), .user_arlen (axi_if.master_if[0].arlen), .user_arburst (axi_if.master_if[0].arburst), .user_araddr (axi_if.master_if[0].araddr), .user_arvalid (axi_if.master_if[0].arvalid), .user_arready (axi_if.master_if[0].arready), .user_awid (axi_if.master_if[0].awid), .user_awsize (axi_if.master_if[0].awsize), .user_aw ... "
The following 32-bit expression is connected to 16-bit port "delay_y_value"
of module "axi_mm_master_top", instance "aximm_ll_msr".
Expression: MASTER_DELAY_Y_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_master_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 261
"axi_mm_master_top aximm_ll_msr( .clk_wr (aximm_top_tb.msr_wr_clk), .rst_wr_n (axi_if.master_if[0].aresetn), .tx_online (llink_m_tx_online), .rx_online (llink_m_tx_online), .init_ar_credit (8'b0), .init_aw_credit (8'b0), .init_w_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_m1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_m1.data_out_f[(80 - 1):0]), .user_arid (axi_if.master_if[0].arid), .user_arsize (axi_if.master_if[0].arsize), .user_arlen (axi_if.master_if[0].arlen), .user_arburst (axi_if.master_if[0].arburst), .user_araddr (axi_if.master_if[0].araddr), .user_arvalid (axi_if.master_if[0].arvalid), .user_arready (axi_if.master_if[0].arready), .user_awid (axi_if.master_if[0].awid), .user_awsize (axi_if.master_if[0].awsize), .user_aw ... "
The following 32-bit expression is connected to 16-bit port "delay_z_value"
of module "axi_mm_master_top", instance "aximm_ll_msr".
Expression: MASTER_DELAY_Z_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_master_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 350
"axi_mm_slave_top aximm_ll_slave( .clk_wr (aximm_top_tb.slv_wr_clk), .rst_wr_n (axi_if.slave_if[0].aresetn), .tx_online (llink_s_tx_online), .rx_online (llink_s_tx_online), .init_r_credit (8'b0), .init_b_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_s1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_s1.data_out_f[(80 - 1):0]), .user_arid (axi_if.slave_if[0].arid), .user_arsize (axi_if.slave_if[0].arsize), .user_arlen (axi_if.slave_if[0].arlen), .user_arburst (axi_if.slave_if[0].arburst), .user_araddr (axi_if.slave_if[0].araddr), .user_arvalid (axi_if.slave_if[0].arvalid), .user_arready (axi_if.slave_if[0].arready), .user_awid (axi_if.slave_if[0].awid), .user_awsize (axi_if.slave_if[0].awsize), .user_awlen (axi_if.slave_if[0].awlen), .u ... "
The following 32-bit expression is connected to 16-bit port "delay_x_value"
of module "axi_mm_slave_top", instance "aximm_ll_slave".
Expression: SLAVE_DELAY_X_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_slave_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 350
"axi_mm_slave_top aximm_ll_slave( .clk_wr (aximm_top_tb.slv_wr_clk), .rst_wr_n (axi_if.slave_if[0].aresetn), .tx_online (llink_s_tx_online), .rx_online (llink_s_tx_online), .init_r_credit (8'b0), .init_b_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_s1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_s1.data_out_f[(80 - 1):0]), .user_arid (axi_if.slave_if[0].arid), .user_arsize (axi_if.slave_if[0].arsize), .user_arlen (axi_if.slave_if[0].arlen), .user_arburst (axi_if.slave_if[0].arburst), .user_araddr (axi_if.slave_if[0].araddr), .user_arvalid (axi_if.slave_if[0].arvalid), .user_arready (axi_if.slave_if[0].arready), .user_awid (axi_if.slave_if[0].awid), .user_awsize (axi_if.slave_if[0].awsize), .user_awlen (axi_if.slave_if[0].awlen), .u ... "
The following 32-bit expression is connected to 16-bit port "delay_y_value"
of module "axi_mm_slave_top", instance "aximm_ll_slave".
Expression: SLAVE_DELAY_Y_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_slave_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 350
"axi_mm_slave_top aximm_ll_slave( .clk_wr (aximm_top_tb.slv_wr_clk), .rst_wr_n (axi_if.slave_if[0].aresetn), .tx_online (llink_s_tx_online), .rx_online (llink_s_tx_online), .init_r_credit (8'b0), .init_b_credit (8'b0), .tx_phy0 (aximm_top_tb.intf_s1.data_in_f[(80 - 1):0]), .rx_phy0 (aximm_top_tb.intf_s1.data_out_f[(80 - 1):0]), .user_arid (axi_if.slave_if[0].arid), .user_arsize (axi_if.slave_if[0].arsize), .user_arlen (axi_if.slave_if[0].arlen), .user_arburst (axi_if.slave_if[0].arburst), .user_araddr (axi_if.slave_if[0].araddr), .user_arvalid (axi_if.slave_if[0].arvalid), .user_arready (axi_if.slave_if[0].arready), .user_awid (axi_if.slave_if[0].awid), .user_awsize (axi_if.slave_if[0].awsize), .user_awlen (axi_if.slave_if[0].awlen), .u ... "
The following 32-bit expression is connected to 16-bit port "delay_z_value"
of module "axi_mm_slave_top", instance "aximm_ll_slave".
Expression: SLAVE_DELAY_Z_VALUE
Instantiated module defined at:
./0.9.1/llink/dv/aximm/regression/test_000__tb_mf2_sf2__addr_width_32/aximm_ll_dut/axi_mm_slave_top.sv",
25
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 622
"marker_gen marker_gen_im( .user_marker (tx_mrk_userbit_master[3:0]), .clk (aximm_top_tb.msr_wr_clk), .rst_n (axi_if.master_if[0].aresetn), .local_rate (1), .remote_rate (1));"
The following 32-bit expression is connected to 4-bit port "local_rate" of
module "marker_gen", instance "marker_gen_im".
Expression: 1
Instantiated module defined at:
./0.9.1/llink/dv/aximm/../../../common/dv/marker_gen.sv",
24
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 622
"marker_gen marker_gen_im( .user_marker (tx_mrk_userbit_master[3:0]), .clk (aximm_top_tb.msr_wr_clk), .rst_n (axi_if.master_if[0].aresetn), .local_rate (1), .remote_rate (1));"
The following 32-bit expression is connected to 4-bit port "remote_rate" of
module "marker_gen", instance "marker_gen_im".
Expression: 1
Instantiated module defined at:
./0.9.1/llink/dv/aximm/../../../common/dv/marker_gen.sv",
24
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 633
"marker_gen marker_gen_is( .user_marker (tx_mrk_userbit_slave[3:0]), .clk (aximm_top_tb.slv_wr_clk), .rst_n (axi_if.slave_if[0].aresetn), .local_rate (1), .remote_rate (1));"
The following 32-bit expression is connected to 4-bit port "local_rate" of
module "marker_gen", instance "marker_gen_is".
Expression: 1
Instantiated module defined at:
./0.9.1/llink/dv/aximm/../../../common/dv/marker_gen.sv",
24
Use +lint=PCWM for more details.
Warning-[PCWM-W] Port connection width mismatch
./0.9.1/llink/dv/aximm/hdl_interconnect/aximm_DUT_wrapper.sv, 633
"marker_gen marker_gen_is( .user_marker (tx_mrk_userbit_slave[3:0]), .clk (aximm_top_tb.slv_wr_clk), .rst_n (axi_if.slave_if[0].aresetn), .local_rate (1), .remote_rate (1));"
The following 32-bit expression is connected to 4-bit port "remote_rate" of
module "marker_gen", instance "marker_gen_is".
Expression: 1
Instantiated module defined at:
./0.9.1/llink/dv/aximm/../../../common/dv/marker_gen.sv",
24
Use +lint=PCWM for more details.
All warnings (except those inside AIB) have been cleaned up as of 0.9.3.
Nij to update this with Intel library synthesis
Analyzing unused pipeline flops in the final design causing check_design warnings. Will close this after root causing this.
Tried this on single-channel case in 0.9.6 : only see these warnings now
Inputs/Outputs 1
Unconnected ports (LINT-28) 1
Cells 41
Cells do not drive (LINT-1) 41
- unconnected port is m_gen2_mode
- _reg_reg are PIPELINE registers that are not used on the master side is not getting optimized by the synthesis - this might need a separate issue to look at this.
- To confirm the post-synthesis functionality ran a gate-level sim: replaced master from 1-channel AXIMM case with synthesized netlist and re-ran UVM directed_test this passed
uit count : 0 of 5
** Report counts by severity
UVM_INFO : 19
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[AIB ENV CFG] 1
[MASTER CFG] 1
[MAXQUITSET] 1
[SLAVE CFG] 1
[directed_test] 11
[final_phase] 1
[new] 3
