spi-aib: Add chiplet user status and chiplet user control registers to the SPI follower

[Dave Kehlet]

1. Add readable user status registers to the SPI follower. Sixteen 32b registers are connected to a user_status[15:0][31:0] port from the chiplet core to the SPI follower module. The user_status[n][31:0] is sampled when the SPI follower decodes the address for “n.” The chiplet user needs to ensure that user_status[n][31:0] is stable when SPI follower samples. See the figure for the user_status SPI follower addresses.
2. Add writable and readable user control registers to the SPI follower. 256 32b registers are connected to a user_control[255:0][31:0] port from the SPI follower module to the chiplet core. The chiplet core is responsible for sampling user_control[][] when it is stable.
3. The user status and user control registers are a design compile time selection, to be included or not included.
   

[Dave Kehlet]

Further discussion: can the application use the existing 3rd AVMM port with a read/write register block? Would avoid the change above.

[Dave Kehlet]

Request withdrawn. User will use the existing AVMM ports.