[question] Why aren't there separate elements for module declaration and module instance?
yurivict opened this issue · comments
In one file I have 2 module definitions, one of the modules is instantiated twice in the top-level module.
Based on the callbacks from UHDM both instances are translated into module_inst objects, but both module_inst objects also contain the entirety of the module definition, such that the entire second module is contained twice in the top-level module.
The top-level module definition is also represented as module_inst, despite the fact that it is only a definition, not an instance.
Is there a way to prevent instance explosion and to have separate module definitions and instances?
Verilog is converted to UHDM using surelog file.sv -parse -d uhdm.
Please submit an actual verilog file as an example, not just a description.
Also cut and paste the piece of UHDM dump that you don't understand.
The Elaboration tree is "elaborated", meaning there is actual duplication, Parameter overloading could change the size of the objects in the sub instances, or generate statements in the sub instances could make each path unique. Hence the duplication.
You can always maintain a set of objects you visited. But most likely your algorithm will miss subtle differences that can happen in each instance path.