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chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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Missing width for signed datatype while parsing

anadishukla opened this issue · comments

commented

Expected to have width defined for output sum as well.

VERILOG Code:
module add(
input [31:0] a,b,
output signed [31:0] sum
);
assign sum = a + b ;
endmodule

UHDM equivalent code:
====== UHDM =======
design: (work@add)
|vpiName:work@add
|uhdmallPackages:
_package: builtin, parent:work@add
|vpiDefName:builtin
|vpiFullName:builtin
|uhdmallClasses:
_class_defn: (builtin::array)
|vpiName:builtin::array
|vpiFullName:builtin::builtin::array
|uhdmallClasses:
_class_defn: (builtin::queue)
|vpiName:builtin::queue
|vpiFullName:builtin::builtin::queue
|uhdmallClasses:
_class_defn: (builtin::string)
|vpiName:builtin::string
|vpiFullName:builtin::builtin::string
|uhdmallClasses:
_class_defn: (builtin::system)
|vpiName:builtin::system
|vpiFullName:builtin::builtin::system
|uhdmallModules:
_module: work@add, file:/home/anadi/Desktop/synthesis_code/surelog-inferencing/comparer/test_dir/verilog/test_signed/test.v, line:1, parent:work@add
|vpiDefName:work@add
|vpiFullName:work@add
|vpiPort:
_port: (a), line:2
|vpiName:a
|vpiDirection:1
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (a), line:2
|vpiName:a
|vpiFullName:work@add.a
|vpiPort:
_port: (b), line:2
|vpiName:b
|vpiDirection:1
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (b), line:2
|vpiName:b
|vpiFullName:work@add.b
|vpiPort:
_port: (sum), line:3
|vpiName:sum
|vpiDirection:2
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (sum), line:3
|vpiName:sum
|vpiFullName:work@add.sum
|vpiContAssign:
_cont_assign: , line:6
|vpiRhs:
_operation: , line:6
|vpiOpType:24
|vpiOperand:
_ref_obj: (a), line:6
|vpiName:a
|vpiFullName:work@add.a
|vpiOperand:
_ref_obj: (b), line:6
|vpiName:b
|vpiFullName:work@add.b
|vpiLhs:
_ref_obj: (sum), line:6
|vpiName:sum
|vpiFullName:work@add.sum
|vpiNet:
_logic_net: (a), line:2
|vpiNet:
_logic_net: (b), line:2
|vpiNet:
_logic_net: (sum), line:3
|uhdmtopModules:
_module: work@add (work@add), file:/home/anadi/Desktop/synthesis_code/surelog-inferencing/comparer/test_dir/verilog/test_signed/test.v, line:1
|vpiDefName:work@add
|vpiName:work@add
|vpiPort:
_port: (a), line:2, parent:work@add
|vpiName:a
|vpiDirection:1
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (a), line:2, parent:work@add
|vpiName:a
|vpiFullName:work@add.a
|vpiRange:
_range: , line:2
|vpiLeftRange:
_constant: , line:2
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
_constant: , line:2
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
_port: (b), line:2, parent:work@add
|vpiName:b
|vpiDirection:1
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (b), line:2, parent:work@add
|vpiName:b
|vpiFullName:work@add.b
|vpiPort:
_port: (sum), line:3, parent:work@add
|vpiName:sum
|vpiDirection:2
|vpiLowConn:
_ref_obj:
|vpiActual:
_logic_net: (sum), line:3, parent:work@add
|vpiName:sum
|vpiFullName:work@add.sum
|vpiContAssign:
_cont_assign: , line:6
|vpiRhs:
_operation: , line:6
|vpiOpType:24
|vpiOperand:
_ref_obj: (a), line:6
|vpiName:a
|vpiFullName:work@add.a
|vpiActual:
_logic_net: (a), line:2, parent:work@add
|vpiOperand:
_ref_obj: (b), line:6
|vpiName:b
|vpiFullName:work@add.b
|vpiActual:
_logic_net: (b), line:2, parent:work@add
|vpiLhs:
_ref_obj: (sum), line:6
|vpiName:sum
|vpiFullName:work@add.sum
|vpiActual:
_logic_net: (sum), line:3, parent:work@add
|vpiNet:
_logic_net: (a), line:2, parent:work@add
|vpiNet:
_logic_net: (b), line:2, parent:work@add
|vpiNet:
_logic_net: (sum), line:3, parent:work@add