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chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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Create SystemVerilog Constraints Model

alaindargelas opened this issue · comments

commented

Capture all the objects, classes, groups pertinent to the SystemVerilog Constraints in the yaml format.
Create UHDM unit tests (C++) showing proper representation of common constraints constructs (Use existing unit tests as reference, or use Google UnitTest framework to capture unit tests).

commented

In https://github.com/alainmarcel/UHDM, read:
README.md
UHDM Presentation
How to create the model (presentation)
Use the following material to ensure compliance to the standard:
Verilog_Object_Model.pdf - Object Model section of the the standard
SystemVerilog 2017 - The standard
includes/vpi_user.h - The VPI Interface
includes/sv_vpi_user.h - The SystemVerilog extensions to the VPI Interface