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chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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Create model for Atomic statement and its inherited objects

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Note, please read the how to create a model document.
It takes several diagrams to complete a single model.

For instance:
"if" which you have to name if_stmt to not conflict with C "if", inherits from atomic stmt and on page 1042 of the LRM has more specification.