cheungxi

black-parrot

A Linux-capable RISC-V multicore for and by the world

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

fastvdma

Antmicro's fast, vendor-neutral DMA IP in Chisel

operating-system

NaxRiscv

VexiiRiscv

Like VexRiscv, but, Harder, Better, Faster, Stronger

dotfiles-public

My personal dotfiles

kenning-pipeline-manager

litex_m2sdr

LiteX based M2 SDR FPGA board.

serv

SERV - The SErial RISC-V CPU

svls

SystemVerilog language server

vpm

Verilog package manager written in Rust

koa-helmet

Important security headers for koa

riscv-elf-psabi-doc

A RISC-V ELF psABI Document

litex-boards

LiteX boards files

discussions

Cross-community issue tracker & discussions / 跨社区工单追踪 & 讨论场所

bootstrap-vue-next

Early (but lovely) implementation of Vue 3, Bootstrap 5 and Typescript

circuitpython

CircuitPython - a Python implementation for teaching coding with microcontrollers

kianRiscV

RISC-V Linux SoC, marchID: 0x2b

migen

A Python toolbox for building complex digital hardware

design-material

Design material for indie hackers

turbo9

Turbo9 - Pipelined 6809 Microprocessor IP

NOP-SoC

System-on-chip design for NOP in NSCSCC 2023.

primevue

Next Generation Vue UI Component Library

gtkwave-filter-process-RISC

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

gtkwave-filter-process

A tool to decode RISC-V and LoongArch instructions in gtkwave

loongchip

An implementation of LoongArch32 Reduced architecture using verilog and verilator with 5-stage pipeline, inherited from chiplab.

ucore_la32_docs

CompressedLUT

A tool to generate optimized hardware files for univariate functions.

AACircuit

Draw circuits using ASCII