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chestnut-Q / SimRISCV

A simple CPU implementation of 5-stage RISC-V pipeline.

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SimRISCV

A simple 5-stage pipeline CPU implementation.

Features supported: Exception and Interrupt Handling, Paging, BHT, Cache and VGA.

Course project of Computer Organization, 2022 Fall at THU.

Contributors: 滕嘉彦，秦若愚，程子睿

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A simple CPU implementation of 5-stage RISC-V pipeline.

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