Chaitravi Chalke's repositories
Edge-Detection-Using-ML
Keras implementation of an architecture similar to DexiNed.
Semantic_Segmentation
Keras and Tensorflow implementation of some renowned architectures.
Code_Challenge
Image Processing
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
ESP32-S2_PCB-Design
A New PCB Design for ESP32-S2 Board
fsm
Finite State Machine Designer
Intro_to_CV
SRA's seminar on Introduction to Computer Vision Fundamentals
neurolab-hardware
Neurolab Hardware
openvino_notebooks
📚 Jupyter notebook tutorials for OpenVINO™
paymentgateway-standalone
Demo rest application with in memory database
payments-ui
payments-ui for openshift version
pslab-hardware
PSLab Hardware Design and Schematics https://pslab.io
RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
v6d
vineyard (v6d): an in-memory immutable data manager. (Project under CNCF)