UART lite modifications
cfelton opened this issue · comments
Christopher Felton commented
The following clean-up needs to be done to the UART module.
- Change the fifo port interface to use a single
fifobus
. The write side of theFIFOBus
will write to the TX fifo and the read side of thefifobus
will read from the RX fifo. Internally the TX read and RX write will be accessed via anotherFIFOBus
interface. - Update the doc strings to use the Google doc format.
- Add documentation to the sphinx docs, bare minimum include the autodocs of the
uartlite
module. - Make sure the code is PEP8.
Pranjal Agrawal commented
- Done, although this need to be done for other modules too.
- Doc Strings updated.
- Sphinx Docs added
- The code is already mostly PEP 8