cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

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fifo_syncers cleanup

cfelton opened this issue · comments

The fifo_syncers.py module needs a little cleanup:

  1. remove the m_ from the functions (myhdl module names).
  2. PEP8 the code, make the signal and variable names full words.
  3. make the resync parameterizable sync_reset(clock, reset_in, reset_out, synclen=2)
  4. add doc-strings.

You will need to search the code and find where the modules were used and updated for the new names.

After the changes, make sure and run the regression tests

cd rhea/test/test_cores/test_fifo
py.test

You can run all the tests from rhea/test but note, currently when running all tests py.test is 10x slower than explicitly running the tests. Use make test to run the tests without py.test.