cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

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[enhancement] create a skipif synthesis tool not available

cfelton opened this issue · comments

Currently majority of the build tests (vendor syn+par) have to be run manually, need to generate tests so the tests will be run automatically. Most of these tests will need to be skipped in travis-ci because the vendor tools (ise, quartus, vivado) will not be available.