It would be nice if clocks could generate architecture specific clock tiles as needed.

[Nick Shaffner]

It would be nice if Rhea's clocks could generate architecture specific clock tiles as needed.

For example, given a hardware_clock specified in a board definition file with a frequency of 12mhz, I want to create a derived_clock of 48mhz (and have rhea automatically set up the clock tile for me)

derived_clock = hardware_clock.create_derived_clock(frequency=48e6)

During vhdl / verilog conversion:

• verification would occur that the frequency could be synthesized by the clock tiles available in the particular part.
• The particular set of multiplies / divides would be set up - and otherwise configuring the clock tile.
• part specific verilog / vhdl would be emitted to specify the clock tile.

Implementation wise, I imagine there would need to be FPGA part specification classes, much like the board files have. I imagine these FPGA classes would contain their various clock resources and contain code to set up the multipliers and dividers and emit the code. I can also imagine the possibility for these FPGA specifications being used in the future for specifying other implementation specific hardware (serdes, clock buffers, etc)

Thoughts?

[Nick Shaffner]

Wait, I seem to have found this already exists in some form in device_clock_mgmt.py.

will give that a try.