cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

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Complete the fifo tests

cfelton opened this issue · comments

In the test_ffifo.py complete the following test cases:

            # @todo: test overflows
            # @todo: test underflows
            # @todo: test write / read same time

Submitted a PR for the new tests. Please review and comment.