cesar-avalos3 / Senior_Design_Capstone

Code prepared for my undergraduate capstone project

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Senior_Design_Capstone

Plan: Implement a RISC-V processor running a pared-down version of Linux. Use the RV64G extension of RISC-V.

See the writeup here for details.

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Code prepared for my undergraduate capstone project

GNU General Public License v3.0

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Language:Verilog 51.1%Language:VHDL 45.6%Language:SystemVerilog 1.4%Language:Shell 0.8%Language:Stata 0.2%Language:Tcl 0.2%Language:TeX 0.2%Language:JavaScript 0.1%Language:Python 0.1%Language:Coq 0.1%Language:Forth 0.0%Language:Batchfile 0.0%Language:1C Enterprise 0.0%Language:Pascal 0.0%