I like RISC-V! I also like HDLs that are more productive than Verilog!
The "official" RISC-V implementations in Bluespec are ... very elaborate and difficult to understand. So, in a quest for better understanding, I've written my own.
Corny5is a fairly literal gloss of the RV32I spec, explicitly optimized for clarity rather than speed or area. It is reasonably speedy but huge. 2 cycles per instruction (CPI).Dinky5is explicitly optimized for area and resources. In particular, it uses half the iCE40 BRAMs of the other designs. 3-4 CPI.Tangy5is intended to be optimized for speed, but to be honest I got kind of bored with it. 2 CPI.Twisty5is a four-thread barrel processor offering roughly four times the throughput of the other cores in about the same area. 4-8 CPI in terms of the system clock.
This is currently intended as an experiment and educational resource, and I make no arguments about this being the bestest RISC-V ever (or even that it is correct).
This is mostly for my reference, when I return to this project later wondering about the results. Numbers may be out of date.
Edit: I've realized two years later that these sizes are underestimates, because my synthesis tools were getting clever and noticing constant bits in the test program I was loading into block RAM. So, these have dropped some instructions that the tools noticed could not occur. Metrics are hard. Anyway, here are the original numbers:
| Core | Target | Shifter | # LCs | fmax (MHz) | MIPS/thread | #threads |
|---|---|---|---|---|---|---|
| Corny5 | hx1k | barrel | 1182 | 53.74 | ~27 | 1 |
| Dinky5 | hx1k | serial | 729 | 60.44 | ~20 | 1 |
| Tangy5 | hx1k | barrel | 836 | 50.95 | ~25 | 1 |
| Twisty5 | hx1k | barrel | 1142 | 84.32 | ~21 | 4 |
Except where noted the contents of this repository are Copyright (C) 2021 Cliff L. Biffle, and are licensed under the terms of the Mozilla Public License 2.0 (see the LICENSE file).
Anything else is marked in the file header.