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caxelos / Embedded-Labs-in-Verilog

embedded project

Repository from Github https://github.comcaxelos/Embedded-Labs-in-VerilogRepository from Github https://github.comcaxelos/Embedded-Labs-in-Verilog

Embedded Project

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embedded project

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Language:LLVM 48.5%Language:VHDL 21.0%Language:HTML 11.8%Language:Verilog 7.8%Language:C++ 6.1%Language:C 3.0%Language:SystemVerilog 0.8%Language:Ada 0.4%Language:Tcl 0.3%Language:JavaScript 0.0%Language:Assembly 0.0%Language:SuperCollider 0.0%Language:Shell 0.0%Language:Stata 0.0%Language:Makefile 0.0%Language:TeX 0.0%Language:CartoCSS 0.0%Language:Forth 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%Language:Coq 0.0%Language:1C Enterprise 0.0%