cathalmccabe

heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

compute_acceleration

Skeletor

Zynq-Design-using-Vivado

This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.

PYNQ-HelloWorld

This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

awslabs

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

RISC-V-On-PYNQ

RISC-V Integration for PYNQ

sha1_pynq

Overlay to use sha1 core on PYNQ board

PYNQ-PRIO

sdbuild

XRT

Xilinx Run Time for FPGA

XIlinx-Workshops

Updated version of the XUP Workshops

awslabs_2018_2

FINN

A Framework for Fast, Scalable Binarized Neural Network Inference

ml_test

IIoT-SPYN

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

chisel-examples

Chisel examples and code snippets

AWS-F1-Developer-Labs

SDAccel_Examples

SDAccel Examples

aws-fpga-app-notes

Application notes for the F1 EC2 Instance

pynq_notebooks

Collection of PYNQ notebooks

PythonUberHDL

Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL

rosetta

Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

BNN-PYNQ

axi_enable

Programmable AXI enable

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

potato

A simple RISC-V processor for use in FPGA designs.