castleberrysam / riscv-cpu

Yet another RISC-V soft core.

Overview

Yet another RISC-V soft core.

Prerequisites

• Building
  • make
  • vivado
• Testing
  • python3
  • xxd
  • binutils-riscv64-linux-gnu (including gdb)
• FPGA synthesis
  • Board based on XC7S50 chip or similar
• Misc
  • gtkwave

Building

Just run make in the top-level directory. The sources in src/ will be built with xsim and the tests in test/ will be built with binutils.

Running/testing

TODO update this section for spike

Every time you run a test in xsim, it should dump a tb_top.vcd file in the sim/ directory with a signal trace for the test. You can examine this vcd file using gtkwave.

Synthesis

TODO update this section for vivado

Test format

Currently only assembly is supported for tests. Every test must begin with a .text directive and end with an invalid instruction (.word 0). The test runner loads the assembled code at address 0x80000000 and executes it until the invalid instruction is encountered.

Task list [3/16]

• [X] Timing constraints/optimization
  • Current target: 80MHz
• [X] Replacement of qemu with spike
• [X] Branch prediction
  • Backward predicted taken, forward predicted not taken
  • 1 cycle miss penalty
• [X] Interrupts/exceptions
• [ ] Integer division
• [X] Memory mapped I/O (peripherals)
• [X] Virtual memory
  • [ ] FENCE.VMA implementation
• [X] Privileged ISA
• [ ] Compressed instructions
• [ ] Atomics
• [X] Caching
• [ ] Floating point
• [ ] Multiple fetch/decode/execute (superscalar)
• [ ] Out-of-order execution
• [ ] Verification using SystemVerilog/UVM
• [X] Synthesis to FPGA