carlosFPGA / HDL_Ciphers

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HDL_Ciphers

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Advanced Encryption Standard

VHDL code for implmenting the Advanced Encryption Standard (AES)

Code related to a series of blog posts on implmenting AES in hardware at https://inmcm.wordpress.com/

Currently Implmented:

  • AES-128 Encryption
  • Dyanmic S-Box Generator

Trivium Stream Cipher

VHDL code for implmenting the Trivium Stream cipher from the eStream project

Currently Implmented:

  • Single Bit-Per-Cycle core
  • Control and Implmentation Logic

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