Hardware and Embedded security course, master degree in cybersecurity Department of Computer Engineering University of Pisa
The projects aims to understand the design flow of an hardware module.
Contents refers to an implementation of an hardware accelerator for a hash function described in full_hash_algorithm_des_sbox.pdf, which consists in an academic hash function.
Details about development and functionalities are described in Project Report.pdf
FPGA family Cyclone V
Modelsim for RTL simulation
Quartus for synthesis, fitting and timing analysis