cambridgehackers's repositories
open-src-cvc
Mirror of tachyon-da cvc Verilog simulator
buildcache
Memoizes execution of build commands
linux-xlnx
The official Linux kernel from Xilinx
bsc-contrib
A place to share libraries and utilities that don't belong in the core bsc repo
llvm-translate
llvm runtime interpreter/translator
verilog-rewrite
A tool to rewrite xilinx synthesized netlists back into non-LUT form (to manually verify elaboration)
Language:CMIT000
cplusplus_draft
C++ standards drafts
Language:C++MIT000
Language:MakefileMIT000
verilator.jeremybennett
A fork of the main Verilator project for development work.
verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.