cambridgehackers

cambridgehackers

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Home Page:http://www.connectal.org/

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cambridgehackers's repositories

connectal

Connectal is a framework for software-driven hardware development.

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fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado

open-src-cvc

Mirror of tachyon-da cvc Verilog simulator

fpgajtag

A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.

bsvtokami

Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.

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xbsv

connectal (formerly called xbsv) contains a utility to generate bit files for Xilinx Zynq devices from BSV programs.

atomicc

Generate Verilog from Atomicc IR files (which are generated from llvm-translate)

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buildcache

Memoizes execution of build commands

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linux-xlnx

The official Linux kernel from Xilinx

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bsc-contrib

A place to share libraries and utilities that don't belong in the core bsc repo

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clang

Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.

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cudd

CUDD: CU Decision Diagram package - unofficial git mirror of http://vlsi.colorado.edu/~fabio/

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llvm

Branch of llvm repository. Use branch release_34atomicc1

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llvm-translate

llvm runtime interpreter/translator

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openocd

packaging branch of openocd

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PYNQ

Python Productivity for ZYNQ with Python board level designs

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verilog-rewrite

A tool to rewrite xilinx synthesized netlists back into non-LUT form (to manually verify elaboration)

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bsc

Bluespec Compiler (BSC)

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cplusplus_draft

C++ standards drafts

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doc

Repository for publishing non-jekyll documentation

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NuSMV

Mirror of NuSMV 2.6.0 from http://nusmv.fbk.eu

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tlaplus

TLC is an explicit state model checker for specifications written in TLA+. The TLA+Toolbox is an IDE for TLA+.

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verilator

Verilator open-source SystemVerilog simulator and lint system

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verilator.jeremybennett

A fork of the main Verilator project for development work.

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verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

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