calyxir / calyx

Intermediate Language (IL) for Hardware Accelerator Generators

https://calyxir.org

calyxir/calyx Issues

New metadata format
Closed 16 days ago2
[Cider 2] Connect to fud2 and the existing test suites
Updated 16 days ago
Cider 2.0 Tracker Issue
Updated 16 days ago3
Separate Out FSM in IR when during TDCC and `compile-static`
Updated 17 days ago17
[Cider 2] Handle memory input/output
Closed 18 days ago4
[Profiling] Tracker Issue for Profiling first steps
Updated 19 days ago4
Add `CONTRIBUTING.md`
Updated 20 days ago1
Docs: refresh the page about the eDSL
Closed a month ago5
Queues: Rethinking our PIFO
Updated a month ago1
Docs: further documentation of `static` features
Updated a month ago
`@data` default assignment optimization does not work on external memories
Closed a month ago3
[fud2] Hypergraph
Updated a month ago2
Use External Libraries To Generate A Single Verilog File
Updated a month ago
Nondeterminism in wire initialization when using `ref` cells.
Closed a month ago
`cell-share` Needs a Timing-Based Heuristic or Cost Model
Updated a month ago1
eDSL: reserved names, nonexistent ports
Updated a month ago2
Toplevel `ref` cells interfere with static promotion
Updated a month ago4
Allowing `invokes` to pass in subtypes to `ref` cells
Updated a month ago1
Do a Better Job At Removing Default Zero Assignments
Updated a month ago
Change `yxi` backend to look for `ref` memories in addition to `@external` memories
Updated 2 months ago1
Toplevel `ref` cells are not kept after `compile_invoke` pass
Updated 2 months ago
Eventually remove `tests/xilinx/cocotb` directory
Updated 2 months ago
Parse error for large constants
Updated 2 months ago2
Report multiple errors
Updated 2 months ago5
Tests are being duplicated
Closed 2 months ago1
[Cider 2.0] Groups taking an extra cycle to exit
Closed 3 months ago4
Support for arbitrary widths greater than 64
Closed 3 months ago4
Default nettype of inline verilog primitives is unset
Closed 3 months ago3
`clk` signal not respecting cycle length
Closed 3 months ago4
Components that do a single read/write to a `seq_mem` generate circular combinational logic
Updated 3 months ago2
Performance Dashboard Planning
Updated 3 months ago2
`seq-mem` outputs `x`s when not explicitly assigning to `write_en`
Updated 3 months ago4
Cannot publish `calyx-lsp`
Closed 3 months ago4
Allow for addition to `par` control blocks in builder
Closed 3 months ago2
Change well-formedness check to allow for toplevel `ref` memories
Closed 3 months ago2
Create an `external-to-ref` pass
Closed 3 months ago3
Calyx LSP Tracker / Wishlist
Updated 3 months ago
Build script fails to update primitives folder
Closed 3 months ago
Reorganize top-level folder
Updated 3 months ago
Calyx website revamp wishlist
Updated 3 months ago4
Make `calyx-py` AXI wrapper `cocotb` testbench accept `yxi` interfaces and dynamic input data
Updated 3 months ago
Default assignments for non-`@data` ports
Closed 3 months ago5
Update Rust version in CI
Closed 4 months ago2
Another Compaction Bug (Sorry)
Closed 4 months ago8
fud dependency on calyx-py
Closed 4 months ago3
Deprecating `@static` and what to replace it with
Closed 4 months ago6
Release 0.7.0 Tracker
Updated 4 months ago
Parameter-dependent attribute values
Updated 4 months ago
Self-contained `fud2` package
Updated 4 months ago1
fud: --to vcd_json flag leads to stack overflor
Closed 4 months ago1