burritoking's starred repositories

VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

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Awesome-Efficient-LLM

A curated list for Efficient Large Language Models

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ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

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sail

Sail architecture definition language

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riscv-isa-sim

Spike, a RISC-V ISA Simulator

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xcrypto

XCrypto: a cryptographic ISE for RISC-V

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scarv-soc

SCARV: a side-channel hardened RISC-V platform

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croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

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riscv-crypto

RISC-V cryptography extensions standardisation work.

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scarv-cpu

SCARV: a side-channel hardened RISC-V platform

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tl-ahb-bridge

This project contains a SystemVerilog implementation of the TileLink UL (Uncached Lightweight) to AHB bridge.

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openai-cookbook

Examples and guides for using the OpenAI API

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codon

A high-performance, zero-overhead, extensible Python compiler using LLVM

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the_silver_searcher

A code-searching tool similar to ack, but faster.

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bazel_rules_hdl

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

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DeepSpeed-MII

MII makes low-latency and high-throughput inference possible, powered by DeepSpeed.

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Dockerize-EDA

[WIP] Dockerize Synopsys/Cadence EDA tools

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awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

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Hardware-Implementation-of-AES-Verilog

Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog

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SystemVerilog-UART

Simple UART transmitter and receiver

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SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

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SoC-Design-DDR3-Controller

DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog

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verilog-i2c

Verilog I2C interface for FPGA implementation

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32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

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sublime_terminal

Launch terminals from the current file or the root project folder

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reprozip

ReproZip is a tool that simplifies the process of creating reproducible experiments from command-line executions, a frequently-used common denominator in computational science.

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rich

Rich is a Python library for rich text and beautiful formatting in the terminal.

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grip

Preview GitHub README.md files locally before committing them.

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