Beast code in Giters

Verilog Indenter. Simple indent program for Verilog source code. Trims end of line white space and indents lines based on nested depth of code blocks.

Language:C++GPL-2.04 10

skid-buffer

Verilog Skid Buffer

Language:VerilogMIT3 10

worker-threads

Simple boss & long lived worker pthread example

Language:CMIT3 2 1

zedboard-vivado-loopback

Zedboard loopback Vivado project for use with the zynq-xdma driver

Language:Verilog3 1 1

cpvdep

Copy Verilog source files and all 'included' dependencies.

Language:ShellMIT2 10

system-rdl-generator

Simple examples of SystemRDL generators

Language:PythonMIT2 10

bitter-build-utility

Build utility for working with Xilinx tools on the command line

Language:PythonMIT1 10

fifo-in-c

FIFO written in C of fixed size that will drop data if full

Language:C1 10

hdl-axi-common

Common HDL AXI modules

Language:SystemVerilogMIT1 10

stream-filter

Streaming Convolutional Filter

Language:VerilogMIT1 10

streaming-convolution

A streaming convolution engine

Language:PythonMIT1 10

verilog-cdc

Selection of Clock Domain Crossing modules

Language:SystemVerilogMIT1 10

zedboard-simple-loopback

Zedboard loopback PlanAhead project for use with the zynq-xdma driver

Language:Verilog1 30